Abstract: A current steering digital to analog converter includes a current source for selectively providing a selected amount of current to an output in response to input data. The current source includes a selected number of sub-current sources for selectively providing fractions of the selected amount of current to the output. Compensation current sources each provide a selected amount of compensation current to the output. Compensation control circuitry, in response to the input data, selectively activates and de-activates selected ones of the sub-current sources and the compensation current sources to provide current compensation at the output.

Abstract: A quasi-differential power amplifier and method are disclosed that enhance drive capability and dynamic range by driving a right, left and common terminals with a right channel output signal, a left channel output signal, and a common mode output signal that are each a combination of the left and right channel input signals. In addition, the common mode output signal may be used as feedback so that the left and right channel output signals so that these signals are dependent upon feedback from the common mode output signal. The quasi-differential power amplifier may include a first amplifier driving the left channel output signal, a second amplifier driving the right channel output signal, and a third amplifier driving the common mode output signal. In one application, the quasi-differential amplifier may be used to drive three-wire stereo headphones for use in small portable stereo systems.

Abstract: A system 100 including a radio receiver 101/108 and switched mode circuitry 114/115 operating at a selected switching frequency is disclosed. Circuitry 207–209 sets the switching-circuitry of the switched mode circuitry 114/115 as a function of a frequency of a signal being received by a radio receiver 101/108.

Abstract: An adaptive clock throttle 600 interfacing a clock generator 601 generating a high speed clock and a processing engine 602 operating in response to a processing clock. Adaptive clock throttle 600 generates a plurality of lower speed clocks from the high speed clock, estimates a duty cycle of the processing engine, and selectively gates one of the lower speed clocks to the processing engine as the processing clock to increase the duty cycle of the processing engine.

Abstract: An ultrahigh molecular weight polyethylene material is utilized in a railroad flangeway to reduce the wear of a railroad crossing base.

Abstract: A digital to analog converter including a noise shaping modulator for modulating an input digital data stream, a plurality of output elements for generating a plurality of intermediate data streams from a modulated output stream from the modulator, and an output summer for summing the intermediate data streams to generate an output analog stream. The noise shaping modulator balances an edge transition rate of the output elements, such that the edge transition rate of two selected elements is approximately equal.

Abstract: A method of performing digital to analog conversion includes generating a pulse width modulated data stream and another pulse width modulated data stream, encoding patterns of the pulse width modulated data stream selected to minimize distortion in the another pulse width modulated stream caused by edges in the pulse width modulated data stream. The pulse width modulated data stream and the another pulse width modulated data stream are converted into an analog signal and another analog signal converting in corresponding digital to analog conversion elements and the analog signal and the another analog signal are summed to generate an analog output signal.

Abstract: An integrator stage for use in a delta sigma modulator includes an operational amplifier, an integration capacitor coupling an output of the operational amplifier and a summing node at an input of the operational amplifier, and a feedback path. The feedback path includes first and second capacitors having first plates coupled electrically in common at a common plate node and switching circuitry for sampling selected reference voltages onto second plates of the capacitors during a sampling phase. The integrator stage further includes a switch for selectively coupling the common plate node and the summing node during an integration phase.

Abstract: A single chip audio system 100 includes a bus interface 101, digital to analog converters 110, an analog mixer 115, and analog spatial enhancement circuitry 7500. Digital to analog converters 110 convert digital audio data received through bus interface 101 into analog signals. Analog mixer 115 mixes signals received from digital to analog converters 110 with an analog signal received from an external source. Analog spatial enhancement circuitry 7500 enhances first and second mixed analog signals output from analog mixer 115.

Abstract: A driver circuit includes an operational amplifier having an input and an output coupled by a feedback element. A voltage level shifter generates a voltage drop from the operational amplifier output to the operational amplifier input with a current source transistor setting a current controlling the voltage drop across the feedback element. A chopper circuit shifts flicker noise generated by the current source transistor to a higher frequency spectrum.

Abstract: A debugging subsystem for testing a system-on-a-chip includes an embedded processor and memory and includes at least one debugging subblock monitors a bus between the processor and the memory to detect selected triggering events, counts the number of triggering events detected and when the number of triggering events reaches a predetermined threshold, generates a debugging signal.

Abstract: A delta-sigma modulator for driving an output stage is disclosed. The delta-sigma modulator operates between first and second voltages and includes a loop filter, a quantizer, and a feedback loop coupling an output of the quantizer and an input of the loop filter. The feedback loop includes compensation circuitry for compensating for variations in the first and second voltages in response to a measured average of the first and second voltages and a measured difference between the first and second voltages. Measuring circuitry measures the average and the difference of the first and second voltages.

Abstract: A jet engine nozzle having a pair of pivoting extension arms and a pair of pivoting shells connected to a jet pipe is provided. The first extension arm is pivotally connected to the jet pipe at a first location, while the second extension arm is pivotally connected to the jet pipe at a second location. Each shell is pivotally connected at both the first and second locations. An axis of rotation associated with the first location is coaxial to an axis of rotation associated with the second location. Independent actuation means are provided to rotate the extension arms and the shells, thereby enabling adjustment of the thrust-vector angle or the exhaust area of the nozzle.

Abstract: A method of processing a stream of encoded units of data samples includes the step of calculating a sample advantage using timing information embedded in selected ones of the encoded units, the sample advantage representing a time difference in number of samples between the presentation of a reference sample and the availability of the reference sample. A number of phantom samples substantially equal to the number of samples represented by the calculated sample advantage are queued and then output from the queue at a selected rate. Substantially simultaneous with the outputting of the phantom samples from the queue, at least some data samples of at least one encoded unit are decoded and queued behind the phantom samples.

Abstract: A method of testing an integrated circuit including the steps of observing a selected parameter at a selected test mode to detect an error. The current to the integrated circuit is stepped from a reference level by selected amount.

Abstract: A digital to analog converter including an input for receiving an input signal, a ramp generator, and a delta-sigma modulator responsive to the input signal and an output of the ramp generator. An order of a noise shaping transfer function of the delta-sigma modulator is response to a level of the output of the ramp generator.

Abstract: System and method for dynamic delivery of services and applications from a server to mobile computing devices in a wireless proximity framework. This wireless proximity framework allows users of mobile computing devices to dynamically access services and applications available in a given geographic area without preinstalling software for each service or application. Further, the wireless proximity framework allows developers to more quickly and easily adapt existing non-wireless services for use by heterogeneous mobile computing devices. Still further, the wireless proximity framework allows for services and applications to be delivered in a customized manner to each mobile computing device.

Abstract: A low power programmable digital filter integrated circuit architecture has a programmable front end servicing up to 4 digital sources. Changing the programming of the front end permits digital outputs from different sensor types to be accommodated. Digital filtering is accomplished using a digital signal processor that is programmable to accommodate different decimation ratios. A serial data output register receives the filtered digital signals and provides them to an output port. The digital filter integrated circuit may be connected in a token passing configuration with other digital filter integrated circuits to increase the number of sources accommodated.

Abstract: A math coprocessor 1300 includes a multiply-accumulate unit 1600. Multiplier-accumulate unit 1600 includes a multiplier array 1603 for selectively multiplying first and second operands, the first and second operands having a data type selected from the group including floating point and integer data types. An adder 1604 selectively performs addition and subtraction operations on third and fourth operands, the third and fourth operands selected by multiplexer circuitry from the contents of a set of associated source registers, data output from multiplier array 1603 and data output from adder 1604.

Abstract: A method of decoding an encoded bitstream. The method includes performing a table lookup. Addresses into the table are generated using selected numbers of bits drawn from the bitstream in response to values stored in the table entries. A table entry may contain an index offset and a number of bits to extract from the bitstream. Alternatively, the table entry may contain the decode result. The value of a result tag in the entry signals which of the alternatives is contained in the entry. The table is recursively accessed until a portion of the bitstream is decoded. Any remaining portion of the bitstream is decoded similarly. An initial index into the table is determined from a number of bits of the bitstream corresponding to the length of the smallest code word in the codetable used to encode the bitstream.