Abstract: A math coprocessor 1300 includes a multiply-accumulate unit 1600. Multiplier-accumulate unit 1600 includes a multiplier array 1603 for selectively multiplying first and second operands, the first and second operands having a data type selected from the group including floating point and integer data types. An adder 1604 selectively performs addition and subtraction operations on third and fourth operands, the third and fourth operands selected by multiplexer circuitry from the contents of a set of associated source registers, data output from multiplier array 1603 and data output from adder 1604.

Abstract: A method of decoding an encoded bitstream. The method includes performing a table lookup. Addresses into the table are generated using selected numbers of bits drawn from the bitstream in response to values stored in the table entries. A table entry may contain an index offset and a number of bits to extract from the bitstream. Alternatively, the table entry may contain the decode result. The value of a result tag in the entry signals which of the alternatives is contained in the entry. The table is recursively accessed until a portion of the bitstream is decoded. Any remaining portion of the bitstream is decoded similarly. An initial index into the table is determined from a number of bits of the bitstream corresponding to the length of the smallest code word in the codetable used to encode the bitstream.

Abstract: A switching element including first, second and third ports each comprising a plurality of lines is disclosed. A first memory cell includes a storage element, a first pass gate for selectively coupling a first line of the first port to the storage element, a second pass gate for selectively coupling a first line of the second port to the storage element, and a third pass gate for selectively coupling a first line of the third port to the storage element. A second memory cell includes a storage element, a first gate for selectively coupling a second line of the first port to the storage element, a second pass gate for selectively coupling a second line of the second port to the storage element, and a third pass gate for selectively coupling a second line of the third port to the storage element.

Abstract: Digital tone controls 500 include a first path 502 including a digital filter 504 and a scaler 505 for controlling a level of a low frequency component of a received digital audio signal. A second 502 includes a digital filter 504 and a scaler 505 for controlling a level of a high frequency component of the received digital audio signal. A third path 503 includes a scaler 506 for controlling a level of an unfiltered component of the received audio signal. A summer 507 adds a contribution from each of the paths to generate a composite signal having a selected gain-frequency response.

Abstract: Transmissions within a communication channel utilized by devices of a computer network that are outside of a device's designated time slot are accommodated through the use of a clear channel assessment time. The clear channel assessment time takes into account the device's designated transmission time slot within the communication channel with respect to those of other network devices. Thus, the clear channel assessment time may be a time period that is the product of a predetermined clear channel waiting time and a numerical representation of the difference between the device's designated transmission time slot within the communication channel and that of another network device that completed a preceding transmission.

Abstract: A signal processing integrated circuit has having a chopper stabilized, multistage, feedforward amplifier and a delta sigma analog to digital converter. Filtering of the output of the output from the analog to digital converter comprises a sinc5 filter and a sinc3 filter. The sinc3 filter may be bypassed. A rough buffer permits quick charging of a sample and hold capacitor during part of the charge cycle and slower but more accurate charging during the remainder of the charge cycle.

Abstract: A packet header for use in information packets transmitted within a computer network includes a protocol extension field that indicates changes of field values and/or lengths within the header. In one embodiment, the protocol extension field includes two bits. The value of the protocol extension field indicates whether or not the packet header has been altered: 00 indicates no alterations, 01 or 10 indicate a predetermined change in the content and/or length of the header, and 11 indicates dynamic negotiation of the field values and/or size. Such packets may be used in a communication protocol for the computer network.

Abstract: A method of testing an integrated circuit includes setting a guardbanded limit for a parameter associated with an embedded node, a deviation from the guardbanded limit under a set of test conditions correlated with a failure of the integrated circuit across a range of operating conditions. A test is performed under the test conditions to detect deviations of the parameter from the guardbanded limit to detect failures of the integrated circuit over the range of operating conditions.

Abstract: A pulse width modulator includes at least one input for receiving an input signal and pulse width modulation circuitry for generating a pulse width modulated stream and another pulse width modulated stream. The pulse width modulated stream and the another pulse width modulated stream are nominally out of phase and together represent the received input signal. A summer sums the pulse width modulated stream and the another pulse width modulated stream to generate an analog output signal.

Abstract: A multi-channel digital audio decoder which receives an encoded audio signal having at least two channels and which decodes the audio signal. The digital audio decoder includes an input, which receives the encoded audio signal and a processor, which receives the encoded audio signal from the input. The processor decodes the encoded audio signal and provides decoded digital audio data. Also included is a buffer, which receives the decoded digital audio data from the processor. The buffer has a first-channel portion and a second-channel portion which have unequal sizes.

Abstract: A portable radio telephone handset includes the capability of operating as a data transfer terminal as well as an analog cellular telephone subscriber station. Two modes of operation are available in the handset, an analog cellular communication mode and a Cellular Digital Packet Data (CDPD) mode. A paging function for incoming analog cellular communication is carried out on a CDPD channel. The handset distinguishes between paging signals identifying CDPD mode communications and paging signals identifying analog cellular communications. The handset automatically preempts CDPD communications in favor of analog cellular communications such as those carried out in an AMPS configuration. To maintain the security of the handset ID, AMPS communications can be set up and controlled using CDPD control channels.

Abstract: An integrator stage for use in a delta sigma modulator includes an operational amplifier, an integration capacitor coupling an output of the operational amplifier and a summing node at an input of the operational amplifier, and a feedback path. The feedback path includes first and second capacitors having first plates coupled electrically in common at a common plate node and switching circuitry for sampling selected reference voltages onto second plates of the capacitors during a sampling phase. The integrator stage further includes a switch for selectively coupling the common plate node and the summing node during an integration phase.

Abstract: A scheme for wireless local area networks provides multimedia extensions for high rate applications. Some of the main extensions provided are the following: The MAC header is extended to include the components for multimedia support. The network topology extensions include tighter definition of the PC, peer-peer connections during CFP, alternate PC and proxy PC. The Quality of Service (QoS) related extensions include the simplifying the operation during CFP, support of streams, stream priority, synchronization of TDM transmissions by devices during CFP, dynamic bandwidth management, channel protection using error control coding and negotiable retransmission parameters. By dynamically negotiating for the priority, bandwidth and the retransmission parameters for each stream separately, the latency control is achieved. There are also proposed extensions to the operation of DCF-only stations in order to better their inter-operation with multimedia capable devices.

Abstract: In a signal processing integrated circuit having an analog to digital converter and a digital filter having a plurality of taps separated in time, when starting a conversion after a reset or a change of input channel, the filter will have an incomplete set of input data as the delayed inputs to an output calculation are all zero from the reset operation. After reset, during the time that data are filling up the filter pipeline, the calculation of an output value will give a result that holds information about the input, but does not present the data with the same scaling and frequency content as the fully settled filter. The integrated circuit selectively provides two modes, on that provides only fully settled data from the filter or and another that provides all data from the filter, including unsettled data. Knowledge about the filter coefficients can be utilized by a user or user process to extract information about the input from the unsettled data.

Abstract: A sobriety interlock system having an alcohol detection device electrically connected to a computing device is provided. An electronic circuit is electrically connected between the computing device and an OBD-II port on a machine for receiving data related to operation of the machine. A breath sample is provided by an operator of the machine and the alcohol detection device determines the alcohol concentration of the breath sample. The computing device determines a blood alcohol concentration for the operator based on the breath alcohol concentration, and the computing device prevents or allows operation of the machine based on the level of the blood alcohol concentration. A memory device stores machine operation data received through the OBD-II port.

Abstract: A method of detecting frequency errors exceeding a predetermined limit in a sampled signal includes the step of determining a peak amplitude of the signal at a tone frequency for a first frame of samples of the sampled signals using a filter having a first amplitude versus frequency response. A peak amplitude of signal at the tone frequency is determined for a second frame of samples of the sampled signal using a filter having a second amplitude versus frequency response. A ratio between the peak amplitude of the first frame and the peak amplitude of the second frame is calculated and compared against a threshold to detect frequency errors exceeding the predetermined limit. Among other things, this method decouples the frequency error detection problem from the twist factor estimation problem.

Abstract: A signal generator generates an output signal with a programmable duty cycle and includes a first buffer which generates in response to an input signal an intermediate signal having a selected edge with a voltage slope selected to vary a length of a selected phase of the output signal. A second buffer having a selected input voltage threshold generates the output signal in response to the intermediate signal.

Abstract: A method for transferring data bursts via a synchronous data link includes the step of receiving a burst of packets, each packet including a header and a frame of data compressed at a selected sampling rate and transmitted at a selected bit rate. At least one of the packets of the stream of packets is embedded into a carrier frame including a carrier frame header. The carrier frame is then transmitted via the synchronous link. The data frame is extracted from the carrier frame and decompressed at the sample rate.

Abstract: The invention is a pop-up device adapted to allow for a number of triggering means and a number of special effects upon triggering of the device. The pop-up device may be placed in a hollow section of a cake, which is later iced over so that the candle holder is not visible. In the preferred embodiment, the base of the device supports the pop-up mechanism within a housing. The device is held in a compressed state by a release mechanism. Upon triggering of the release mechanism, the device is released and pushed through the cake or other confection, thereby providing surprise and entertainment. In alternative embodiments, the device is actuated by a drive mechanism or a fuse.

Abstract: A spread spectrum radio receiver configurable for use in both a quadrature phase shift keying (QPSK) and a frequency shift keying (FSK) environment. The receiver may include a programmably selectable zero crossing detector unit for use when the receiver is configured for the FSK environment and/or programmable low pass filters having variable cut-off frequencies. A common local oscillator may be used regardless of whether the receiver is configured for use in the QPSK or FSK environment.