Abstract: An arrangement for tuning a micro-electro-mechanical (MEM) laser center wavelength to exactly match the passband of its associated filter. A dither wavelength locked feedback loop dynamically adjusts the position of the MEM element, and hence the laser, wavelength, to keep it nominally centered at the filter passband peak. The dither wavelength locked feedback loop compensates for many internal variables of the laser, filter, and the MEM with a single mechanism that stabilizes the laser and locks the wavelength to any desired value.

Abstract: A system and method for controlling alignment of laser center wavelengths and filter passband center wavelengths in optical amplifiers for purposes of providing automatic gain control and eliminating unwanted noise. The system and method exploits a wavelength-locked loop servo-control circuit and methodology that enables real time mutual alignment of a laser pump signal having a peaked spectrum function including a center wavelength and a wavelength selective device such as an optical filter implementing a peaked passband function including a center wavelength in an optical amplifier.

Abstract: A system and method for improving optical signal gain efficiencies of semiconductor optical amplifier devices. The system and method exploits a wavelength-locked loop servo-control circuit and methodology that enables real time mutual alignment of the center wavelength of an optical signal having a peaked spectrum function and transmitted through the semiconductor optical amplifier, and a center wavelength of a wavelength selective device such as an optical filter implementing a peaked passband function in an optical system. The wavelength-locked loop servo-control circuit and methodology may be further exploited to control various types of modulation applied to the optical signals transmitted in optical systems.

Abstract: A system and method for automatically attenuating optical signals transmitted in optical systems. The system and method exploits a wavelength-locked loop servo-control circuit and methodology that enables real time mutual alignment of the center wavelength of an optical signal having a peaked spectrum function and transmitted through the optical system, and a center wavelength of a wavelength selective device such as an optical filter element implementing a peaked passband function. The wavelength-locked loop servo-control circuit and methodology particularly is capable of real-time aligning the center wavelength of an optical signal in a range between maximum overlap with the center wavelength of the peaked passband function of the optical filter for maximum transfer of output optical signal by the filter element and minimum overlap with the peaked passband function of the optical filter so that output optical signal may be attenuated in the optical system.

Abstract: A semi-conductor wafer test or burn-in apparatus having spring contacts made from a shape memory metal which plastically deforms under normal test loading and has a transition temperature at or above or at or below the burn-in temperature.

Abstract: A method of forming a metal oxide semiconductor field effect transistor (MOSFET) having a metallic gate electrode that is protected with hanging sidewall spacers during a subsequent gate oxidation process is provided. A semiconductor structure formed by the inventive method is also provided. Specifically, the inventive semiconductor structure includes a semiconductor substrate comprising a patterned gate region formed atop a patterned gate dielectric, the patterned gate region includes at least a metallic gate electrode formed atop a polysilicon gate electrode; hanging sidewall spacers formed on an upper portion of the patterned gate region including the metallic gate electrode; and a thermal oxide layer formed on lower portions of patterned gate region including a portion of the polysilicon gate electrode, but not the metallic gate electrode.

Abstract: A system and method of compensating for optical polarization dispersion effects exhibited in a length of optical fiber in an optical network. The system and method exploits a wavelength-locked loop servo-control circuit and methodology that detects a polarization mode dispersion characteristic of the optical signal and enables real time adjustment of the center wavelength of the optical in manner so as to minimize polarization effects in the optical fiber link. In another embodiment, the wavelength-locked loop servo-control circuit and methodology is implemented for enabling real time physical adjustment, e.g., X-Y dimension strain control, of the optical fiber link itself in accordance with the detected amount of polarization mode dispersion.

Abstract: A process for picking up and moving a microelectronic package during card assembly operations. A clipping lid having a top surface and at least two sides attaches to a substrate via friction where the sides act as leaf springs gripping the substrate. The top surface of the lid provides a clean, smooth, flat surface to which a vacuum probe may be attached. In the preferred embodiment, the lid and sides are formed from an integral piece of stainless steel. Also provided are flares at the bottom of each side to aid in guiding the lid onto the substrate. Protrusions are provided in the sides to prevent the lid from slipping too far onto the substrate and contacting the components mounted to the substrate. Also provided is at least one hole in the top surface to allow the lid to be pried free from the substrate after completion of the steps where vacuum probe movement is required.

Abstract: An apparatus and method for evaluating the performance of a test dielectric material for use as a gate dielectric. The method comprises exposing a coated layer of the dielectric to a concentration of atomic hydrogen. The method may comprise (a) measuring an initial value of interface-state density in the test dielectric, (b) exposing the coated test dielectric to a concentration of atomic hydrogen in a remote plasma, and then (c) measuring a post-exposure value of interface-state density in the test dielectric. Steps (b) and (c) may be repeated with incrementally higher concentrations of atomic hydrogen to determine a rate of change in interface-state density value as a function of atomic hydrogen concentration, which may then be related to the projected charge-to-breakdown or time-to-breakdown of the test dielectric layer when the dielectric is used as the gate dielectric.

Abstract: A system for stressing and monitoring an electrical device, such that the imposed stress conditions may be terminated at electronic speeds, thereby preventing destruction of the device under test. The system includes stress channels each paired with a control and monitor circuit, such that the control and monitor circuit may shut down the stress if a limiting stress level is detected by the control and monitor circuit. A microprocessor is used to communicate via a digital control bus with each of the paired stress channels and control and monitor circuits to determine the status of the stress channel; control the stress input; and enable or disable the control and monitor circuits. A computer is used to communicate with the microprocessor through a serial interface.

Abstract: A semiconductor device having a planar integrated circuit interconnect and process of fabrication. The planar integrated circuit comprises a substrate having a first line wire formed in the substrate, a dielectric layer formed on the substrate, a second line wire formed in the dielectric layer, a contact via formed within the dielectric layer extending through the dielectric layer from the second line wire to the first line wire, and a dummy via which extends into the dielectric layer and is filled with a low dielectric material.

Abstract: A process for obtaining accurate DC convergence in a DC phase of a circuit simulation program for models of field effect transistors (FETs) on a silicon-on-insulator (SOI) substrate. The process comprises running iterations of the DC phase of the circuit simulation program such that error criteria are satisfied, wherein the pseudo-time step changes at each iteration until it reaches a value such that a desired current value is achieved. DC convergence is also achieved by reducing the magnitude of the capacitive and/or charge elements connected to the floating body regions of the field effect transistors on the silicon-on-insulator substrate model during the DC phase to achieve a desired current value.

Abstract: A fixture for holding a workpiece in a machining apparatus comprises at least one opening having at least one flexible side for elastically holding the workpiece and a slot adjacent each of the at least one side for allowing the side to flex.

Abstract: A trench capacitor having an increased surface area. In one embodiment, the trench capacitor is a dual trench capacitor having a first trench and a second trench wherein inner walls of the trenches electrically connect. The invention also includes a single trench capacitor wherein the trench is curved around an axis substantially perpendicular to a substrate surface.

Abstract: A stress-driver circuit for providing a constant voltage (Vce) and a constant current (I=Vin/R) to a bipolar transistor under test. The circuit includes a power source, an op-amp, a FET, and the bipolar transistor. The power source is connected to the bipolar transistor collector. The op-amp has a positive input biased at input voltage (Vin) and a negative input having a feedback loop connected to the bipolar transistor emitter. The op-amp output is connected to the FET gate, the FET drain is connected to the power supply, and the FET source is biased to ground through a first resistor and connected to the base of the bipolar transistor. The second resistor is connected at one end to the bipolar transistor emitter and biased to ground at the other end. An automatic trip circuit may be provided to cut off power to the bipolar transistor if the current at the bipolar transistor collector exceeds a predetermined value.

Abstract: A bed-of-nails type or needle-card type test probe has clusters of parallel buckling beams arranged in a spaced arrangement. The buckling beams are arranged and electrically connected within a cluster so that a contaminant, which may be on the device being tested, does not reduce the accuracy of the test measurements. In particular, the spacing of the buckling beams is such that multiple buckling beams are capable of contacting a single feature on an electronics package to be tested. The buckling beams deflect independently of each other in response to compressive force, and the buckling beams within a cluster are electrically connected in parallel to each other to define redundant, independent conductive paths through the buckling beams. In this way, if a contaminant prevents one of the buckling beams of the cluster from making electrical contact with the feature to be tested, the other one or more of the buckling beams of the cluster will make the required electrical connection.

Abstract: A power booster and current measuring circuit provides a quiet, accurate voltage to a load (such as a transistor during parametric testing) with a load current of up to 1 ampere, and can measure that load current to an accuracy of ±0.1 % over a range of currents extending nine orders of magnitude (e.g., 1 ampere to 10−9 amperes). The load voltage is supplied by a sense driver, a bypass driver, or both. The bypass driver comprises a high-current operational amplifier with a direct feedback loop (e.g., a voltage follower). The sense driver comprises a high-impedance operational amplifier having a feedback loop comprising a high-current operational amplifier connected as a voltage follower and one of a series of sense resistors having different values.

Abstract: The invention provides a PIN diode having a laterally extended I-region. The invention also provides a method of fabricating the inventive PIN diode compatible with modern RF technologies such as silicon-germanium BiCMOS processes.

Abstract: A jig for aligning a wafer-handling system in a calibration location, such as a wafer pickup-dismount location, with respect to a wafer-processing tool. The jig comprises an alignment fixture adapted to be repeatably mounted on the tool and having one or more edge stops. The jig may further comprise an edge-to-center locator adapted to be mounted on the alignment fixture. The edge-to-center locator has a peripheral edge and a center marker that identifies the precise center of the calibration location when the edge-to-center locator edge is positioned in contact with the edge stop or stops. An alignment method for use of the jig is also disclosed.

Abstract: A method for optically measuring lithographic process bias of a minimum feature formed by a lithographic process. The method comprises creating on a substrate an array of elements from which a darkfield optical image is generated and detected, electronic information corresponding to the image is generated and processed, and the difference between the created length versus the nominal length of the elements is calculated to determine lithographic process bias. The darkfield optical image may be a double-lobe optical image, and signal processing may comprise creating a normalized intensity profile to overcome film-thickness dependencies, to which one or more noise-rejecting, edge-detection methods is or are applied to calculate the created length of the elements. A method for using double-lobe darkfield imaging for general edge detection is also disclosed.