Abstract: A semiconductor device having a planar integrated circuit interconnect and process of fabrication. The planar integrated circuit comprises a substrate having a first line wire formed in the substrate, a dielectric layer formed on the substrate, a second line wire formed in the dielectric layer, a contact via formed within the dielectric layer extending through the dielectric layer from the second line wire to the first line wire, and a dummy via which extends into the dielectric layer and is filled with a low dielectric material.

Abstract: An impedance matching system and a network for impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises an adjustable-length transmission line having a length adjusted in proportion to the magnitude of transients on the driver circuit output and an input impedance, which is purely reactive, and is a function of its length. The purpose of the adjustable-length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver circuit to the driver circuit. In the preferred embodiment, the impedance matching network comprises two parallel conductive lines formed on the system card, shorted by a movable stub, and connected in parallel to the driver circuit.

Abstract: A copper-containing, wire-bonding pad structure for bonding to gold wires. The structure includes a nickel-containing film to improve metallurgical characteristics. The structure also has a laminated impurity film within the copper pad, which complexes with the nickel-containing pad to prevent a destructive interaction between nickel and copper at elevated temperatures, or during the lifetime of the device or the wirebond.

Abstract: A process and apparatus for picking up and moving a microelectronic package during card assembly operations. A temporary lid having a top surface and a bottom surface attaches to at least one microchip on a substrate via a double-sided adhesive. The top surface of the lid provides a clean, smooth, flat surface to which a vacuum probe may be attached. After completion of the steps where vacuum probe movement is required, the lid and adhesive may be removed from the at least one microchip by pulling them both off together. No residue is left on the microchips.

Abstract: A wire interconnect structure for electrically and mechanically connecting an integrated circuit chip to a substrate and a process for manufacturing the same. The wire interconnect structure comprises an insulator layer disposed on an integrated circuit chip and an electrically conductive post extending through the insulator layer to the integrated circuit chip. The post has an elongated body, a bottom at one end of the body which is mechanically and electrically connected to the integrated circuit chip, and a top having a spherical shape at the opposite end of the body which extends outward from the insulator layer.

Abstract: A process for estimating a critical dimension of a trench formed by etching a substrate. First, a regression model is constructed for estimating the critical dimension, in which principal component loadings and principal component scores are also calculated. Next, a substrate is etched and spectral data of the etching are collected. A new principal component score is then calculated using the spectral data and the principal component loadings. Finally, the critical dimension of the trench is estimated by applying the new principal component score to the regression model.

Abstract: A vertical channel field effect transistor and a process of manufacturing the same. The vertical channel field effect transistor is disposed on a surface of a substrate and comprises an epitaxial silicon stack having a bottom terminal comprising heavily doped silicon, a channel comprising lightly doped silicon of opposite doping type from the bottom terminal, and a top terminal comprising heavily doped silicon of the same doping type as the bottom terminal. The vertical channel field effect transistor also comprises a gate dielectric layer covering at least a portion of the bottom terminal, the channel, and the top terminal, and a gate in contact with the gate dielectric layer. The gate is positioned adjacent the channel and adjacent at least a portion of the bottom terminal and top terminal. The channel has a thickness between the bottom terminal and the top terminal from about 50 angstroms to about 800 angstroms.

Abstract: A structure and process for a triple damascene interconnection device. The device is formed within a terraced trench formed using damascene techniques within a single, relatively thick dielectric film. The interconnection device formed within the terraced structure includes a plurality of films and is a vertically coherent, redundant structure.

Abstract: A non-volatile random access memory (NVRAM) structure comprising an injector element in a single crystal silicon substrate; an insulator layer over the substrate; a silicon-on-insulator (SOI) layer over the insulator layer; and a sensing element in the SOI layer overlying the injector element. The NVRAM structure may further comprise a gate above the SOI layer, a floating gate in the insulator layer, or both.

Abstract: A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.

Abstract: A calibration wafer for precisely aligning a wafer-handling system that processes a plurality of product wafers. The calibration wafer has radial and thickness dimensions and tolerances equivalent to those of the product wafers and further comprises a first center marker adapted for alignment with a second center marker external to the calibration wafer. The calibration wafer may be a component of a wafer center alignment device for precisely aligning a wafer-handling system in a calibration location in relation to a wafer-processing tool, the device further comprising an alignment jig adapted to be repeatably mounted on the tool and on which the second center marker is located. The calibration wafer is adapted to be positioned so that the first center marker aligns with the second center marker.

Abstract: A structure for enhancing electromigration resistance within a copper film includes impurities laminated within the film and other additives incorporated in the film to form intermetallic compounds. Metal grain boundary growth and metal surface mobility is suppressed within the composite copper film. The present invention provides an alloy seed layer and laminated impurities and provides indium, tin, titanium, their compounds with oxygen, and their complexes with oxygen, carbon, and sulfur, incorporated into other films. Intermetallics are disposed at grain boundaries and reduce copper atom mobility. A further aspect of the present invention is a barrier layer formed by combining additives included in an alloy seed layer with materials otherwise unsuitable for barrier material functions.

Abstract: A semiconductor device or other suitable substrate and method with single or multi layers of buried micro pipes are disclosed. This is achieved by controlling the aspect ratio of trenches as well as controlling the deposition characteristics of the material used to fill the trenches. A buried micro pipe is formed by filling a trench that has a height which is larger than a width thereof, so that the trench filler material lines sidewalls and bottom of the trench, and covers the top of the trench to form the micro pipe within the trench. Another layer can be formed over the filler material and planarized. Alternatively, the filler material itself can be planarized. Forming trenches in the planarized layer, and repeating the above steps forms a second set of buried micro pipes in these new trenches. This forms a semiconductor device having multiple layer of buried micro pipes.

Abstract: A device and method for enabling the reworkability of an integrated circuit comprising a wirebond chip having a bottom surface and a carrier substrate having a first surface and a second surface. The first surface and second surface of the carrier substrate are electrically connected through a series of vias. A bonding agent is used to mechanically attach the wirebond chip to the carrier substrate in addition to wirebonds for electrically connecting the wirebond chip to the substrate. The substrate is attached to a multi-chip module (MCM) by ball grid array (BGA) or controlled collapse chip connection (C4) attaching process.

Abstract: A multi-layer ceramic capacitor and method of manufacturing the capacitor, the capacitor having signal vias surrounded by an area containing a material having a low dielectric constant, the via and surrounding area of low dielectric constant material inserted in a material having a high dielectric constant.

Abstract: A trench capacitor having an increased surface area. In one embodiment, the trench capacitor is a dual trench capacitor having a first trench and a second trench wherein inner walls of the trenches electrically connect. The invention also includes a single trench capacitor wherein the trench is curved around an axis substantially perpendicular to a substrate surface.

Abstract: A method determining the status of a feature (e.g., a semiconductor contact hole or trench) using a measurement imaging tool such as a scanning electron microscope (SEM). The method first assures that the waveform signal obtained from the SEM is reliable. A blanked beam signal, provided in saved images from the SEM, is the basis for a signal quality factor. This signal is provided in the waveform analyzed by the system. The method then analyzes all of the data between the edges of the feature and fits various functions to the data to determine which provides the best fit. Multiple linear regression and the r2 (quality of fit) factor, or some other type of correlation coefficient, are used to determine which function has the best fit. The feature is then characterized based on the particular function chosen and on the correlation factor obtained.

Abstract: A structure and process for a copper-containing, wire-bonding pad structure for bonding to gold wires. The structure includes a nickel-containing film to improve metal lurgical characteristics. The structure also has a laminated impurity film within the copper pad, which complexes with the nickel-containing pad to prevent a destructive interaction between nickel and copper at elevated temperatures, or during the lifetime of the device or the wirebond.

Abstract: A process for making metal lines in BEOL semiconductor devices. The process reduces metal voids in the metal lines. In one embodiment, metal lines, including a top barrier blanket are formed over an interlevel dielectric. An insulating layer having tensile stress is formed over the metal lines. A first compressive oxide layer is formed over the insulating layer, wherein the insulating layer provides a tensile stress on the metal lines and the compressive oxide layer provides a compressive stress on the metal lines resulting in reduction of metal voids. The compressive oxide layer is etched with a first type of gas until the insulating layer is reached. The insulating layer is etched with addition of gases to facilitate end-point detection. This second type of gas is monitored for an emission of species at an intensity level having a specific wavelength optical emission, and the etching is stopped when the intensity level is reached.