Abstract: A process for producing a multi-level semiconductor device having metal interconnections with insulating passivation layers and the product produced thereby. The product and process improve the resistance of the metallization interconnections to extrusion-short electromigration failures by preventing the insulating passivation layers from cracking. The product and process also reduce the level of resistance saturation or the maximum resistance shift caused by electromigration. By replacing wide-line metallization interconnection conducting lines surrounded by insulating passivation layers with two or more narrow, parallel conducting lines having aspect ratios less than or equal to unity with passivation layers located in between, the incidence of passivation cracking and extrusion-short failures is reduced.

Abstract: A method for developing a photomask layout by which an electrical circuit is imaged that includes introducing sub resolution assist features into a photomask layout by (1) sorting selected details of the main electrical circuit undergoing enhancement according to a predetermined order of importance of enhancement of the selected details of the main electrical circuit to the overall performance of the main electrical circuit, (2) establishing a prioritization for sub resolution assist features associated with the selected details of the main electrical circuit based on the predetermined order of importance of the selected details of the main electrical circuit with which the sub resolution assist features are associated, and (3) incorporating sub resolution assist features in the photomask layout in accordance with the established prioritization of the sub resolution features.

Abstract: A wafer metrology structure for measuring both critical dimension features of multiple patterns of a semiconductor device and overlay measurements of one pattern with respect to another. The measurements are readable by a single, one-dimensional scan of a metrology system. The wafer metrology structure includes at least a first feature of a first dimension formed in a first level of the semiconductor device. The first dimension is identical to a first critical dimension of a pattern formed in the corresponding first level. A wafer metrology pattern according to the present invention also includes a second pattern of a second dimension formed in a second level of the semiconductor device. The second pattern includes an aperture superposed over the first feature. The aperture exposes at least the first feature having a critical dimension of the first pattern and thus enables a metrology system to directly measure the first feature through the aperture.

Abstract: A buckling beam probe assembly and a process to make the assembly using insulated metal to hold the vertical beam probe wires. The buckling beam probe assembly electrically connects a test apparatus with contact pads on the surface of a device to be tested. The assembly is formed with a plurality of buckling beam wires each having a head, a body, and a tail. Each of the beam wires is pressed vertically onto the contact pads and buckles laterally to adapt to height differences of the contact pads caused by irregularities on the surface of the device to be tested. A top plate has a first plurality of apertures receiving the heads of the plurality of buckling beam wires. A bottom plate has a second plurality of apertures receiving the tails of the plurality of buckling beams wires. A plurality of intermediate metal sections are positioned between the top plate and the bottom plate.

Abstract: A damascene structure, such as a conductive line or via, having a liner with a roughened surface between the substrate and the conductive fill and, preferably, a smooth bottom. The substrate underneath the liner may also have a roughened sidewall and smooth bottom. Such a structure provides enhanced adhesion between one or more layers of the damascene structure. The damascene structure may be manufactured by applying a photoresist over a substrate top surface, exposing the photoresist under conditions that create a standing wave in the resist, and developing the photoresist to provide a pattern having the desired roughened or serrated outline. The pattern is transferred into the substrate, the liner is applied over the substrate bottom and sidewalls, and the liner is filled with conductive material. A roughened liner surface may be achieved by applying a partial layer of liner material over the substrate, removing a portion of the partial layer, and repeating the application and removal steps.

Abstract: A process for controlling grain growth in the microstructure of thin metal films (e.g., copper or gold) deposited onto a substrate. In one embodiment, the metal film is deposited onto the substrate to form a film having a fine-grained microstructure. The film is heated in a temperature range of 70-100°C. for at least five minutes, wherein the fine-grained microstructure is converted into a stable large-grained microstructure. In another embodiment, the plated film is stored, after the step of depositing, at a temperature not greater than −20° C., wherein the fine-grained microstructure is stabilized without grain growth for the entire storage period.

Abstract: Preferred embodiments for methods of removing an integrated circuit (“IC”) from a substrate, where the IC is attached to the substrate by multiple solder connections are disclosed. One preferred embodiment of the inventive methods provides the steps of heating the IC and substrate to the reflow temperature for the solder connections and pulling the IC from the substrate by means of a vacuum force. Another preferred embodiment of the inventive method provides the step of shearing the IC from the substrate after the substrate and IC are heated, but before solder reflow temperature has been reached, and where the shearing force may be programmed through a computer controlled servomotor. Preferred embodiments of certain apparatus applying the inventive methods for removing an integrated circuit from a substrate are also disclosed.

Abstract: A trench capacitor for use with a substrate. The capacitor has an inner electrode formed above the substrate. The inner electrode has a plurality of metal layers, a dielectric partially surrounding the inner electrode, and an outer electrode partially surrounding the dielectric.

Abstract: A process and apparatus for dynamically adjusting the exposure dose on a photosensitive coating at a localized area within an exposure field in a step-and-scan lithography system. The process and apparatus form a pattern on a photosensitive substrate, such as used in the integrated circuit manufacturing industry. The exposure dose is adjusted at a localized area by a segmented slit system or an array of light-transmitting pixels located across the exposure field. The slit segments or individual pixels are automatically controlled in response to data obtained regarding the uniformity of the projection optics system or the mask pattern.

Abstract: A conditioning tool including a rotary conditioning pad; a lower shaft attached to the conditioning pad; an upper shaft having an upper end and a lower end, the lower end attached to the lower shaft via a flexible coupling; and a motor attached to the upper end of the upper shaft and adapted to rotate the shaft. The tool further includes a mechanism for measuring an angle of the conditioning pad relative to a reference plane. The conditioning tool may further include a conditioning arm, various control mechanisms, and a controller for receiving feedback from the angle measuring mechanism and the various control mechanisms and for controlling the various control mechanisms in response to the feedback. A chemical-mechanical polishing apparatus and a conditioning method for providing a uniform polishing surface of a chemical-mechanical polishing pad are also disclosed.

Abstract: An integrated circuit and method of making the integrated circuit. Air gaps are formed between surfaces of current-conducting lines that face one another and dielectric material disposed between these surfaces of the current-conducting lines. A liner material is applied to these surfaces of the current-conducting lines and, after the dielectric material is introduced between the current-conducting lines, the liner material is removed, for example by etching, leaving air gaps between the current-conducting lines and the dielectric material. These air gaps eliminate or greatly reduce the effect of capacitive currents across the dielectric material between the current-conducting lines.

Abstract: A method for making a metallic pattern that includes redundant photolithography to significantly reduce the occurrence of defects in the metal layer that defines the desired metallic pattern. The presence of contaminants in the photoresist layer during exposure and developing away of portions of a photoresist layer can cause defects in the metal layer that defines the desired metallic pattern. Contaminants in the photoresist layer prevent portions of the photoresist layer from being exposed and developed away, so that portions of the photoresist layer that should be developed away remain in place, thereby causing the development of defects in the metal layer that defines the desired metallic pattern. These contaminants move to different positions during the developing away of the photoresist.

Abstract: A lens assembly with materials that densify and rarefy as a function of radiation dose. The lens assembly can be provided for use in photolithographic exposure tools. The combination of densifying and rarefying materials in the lens elements of exposure tools compensates for changes in the index of refraction of the materials. The lens assembly of the present invention corrects, by design, for radiation-induced changes in the indices of refraction of the lens element materials. By compensating for radiation-induced changes, the lens assembly has a longer useful lifetime.

Abstract: A planarized interleaved capacitor for use with a substrate. The capacitor has a plurality of planarized metal layers formed above the substrate, at least one dielectric layer disposed between the plurality of planarized metal layers, and at least one insulator layer disposed over one of the plurality of metal layers.

Abstract: A method for migrating legacy applications into a new software product architecture using a functional conversion module located within a system controller. The functional conversion module comprises a migration plan shut off. The functional conversion module further comprises three paths or branches through which a functional request can be routed. Functional requests which are not identified in the migration plan are routed through the first path and the functional request is sent to the pre-existing software and executed as requested. Functional requests identified in the migration plan for which the pre-existing software is in control are routed through the second path, and the functional request is sent to the pre-existing software and executed as received. In the background, the functional request is translated for the new software and sent to the new software and executed.

Abstract: A book-like fixture and method for assembly of a plurality of multi-layered ceramic packages including a substrate and a cap. The fixture has a baseplate, a removable tray, an alignment plate for precisely aligning the caps with the substrates, a compression plate, and a plurality of compression devices designed to uniformly distribute compressive force on the plurality of packages. The fixture is preferably adapted for use of removable trays conforming to the Joint Electronics Design Engineering Council Tray Standard. The compression devices preferably have a spring, preferably a detachable leaf spring, and a compression plate placed over each cap. The structure of the fixture allows replacement of the springs and other modifications to allow assembly of multi-layered ceramic packages of differing dimensions. The structure of the fixture also allows stacking one on top of another.

Abstract: An apparatus and method for evaluating the performance of a test dielectric material for use as a gate dielectric. The method comprises exposing a coated layer of the dielectric to a concentration of atomic hydrogen. The method may comprise (a) measuring an initial value of interface-state density in the test dielectric, (b) exposing the coated test dielectric to a concentration of atomic hydrogen in a remote plasma, and then (c) measuring a post-exposure value of interface-state density in the test dielectric. Steps (b) and (c) may be repeated with incrementally higher concentrations of atomic hydrogen to determine a rate of change in interface-state density value as a function of atomic hydrogen concentration, which may then be related to the projected charge-to-breakdown or time-to-breakdown of the test dielectric layer when the dielectric is used as the gate dielectric.

Abstract: A process of etching an oxide layer placed over a nitride layer of a substrate with high selectivity. The process comprises plasma etching the oxide layer of the substrate with a carbon and fluorine-containing gas and with a nitrogen-containing gas. A SixNy species is formed which is deposited on the nitride layer substantially in equilibrium with etching of the nitride layer.

Abstract: A process for forming multilevel metallization structures that improve semiconductor reliability. Multilevel metallization structures are formed through a two-step etch process which alleviates the problem of conductive etch residue forming between metal layers in multilevel structures. The resulting metallization structure has sidewall insulators on selected layers that prevent conductive etch residue from forming between the metal layers. The integration scheme of the present invention is especially applicable to metal-insulator-metal (MIM) capacitors.

Abstract: A method for obtaining equalization voltages that are a fraction of bit line high other than ½ in a DRAM semiconductor circuit, and an associated circuit, in arrangements that include a plurality of block cell arrays with a plurality of complementary pairs of bit lines connected to each block array with control lines to selectively activate a desired array block. Each block uses shared sense amplifiers connected to the pairs of bit lines and there is an equalization circuit connected between each of the bit line pairs of each of the array blocks, between each of the array blocks and the shared sense amplifiers. A charge flow circuit is also connected between each of the bit line pairs of each of the array blocks, between each of the array blocks and the shared sense amplifiers. A charge flow circuit control line is connected to the charge flow circuits for connecting the charge flow circuit to an electrical ground, thereby to act as a discharge circuit or to the bit line high voltage.