Abstract: A device and a method for processing high data rate serial data includes circuitry for recovering a clock based on the high data rate input data stream and for providing the recovered clock to a circuit portion, for example, a portion of a field programmable gate array fabric, to enable the circuit portion to use either a reference clock or the recovered clock for subsequent processing. The invention specifically allows for different circuitry portions to utilize different clocks, including different recovered clocks, for corresponding functions that are being performed. Applications for the present invention are many but include multi-gigabit transceiver, switching devices, and protocol translation devices. More generally, the device and method provide for application specific clock references to be utilized in order to minimize or eliminate timing mismatch in serial data processing.

Abstract: An analog front-end having built-in equalization includes a control module and a tunable gain stage. The control module is operably coupled to provide a frequency response setting based on a channel response of a channel providing high-speed serial data to the analog front-end. The tunable gain stage includes a frequency dependent load and an amplifier input section. The frequency dependent load is adjusted based on the frequency response setting. The amplifier input section is operably coupled to the frequency dependent load and receives the high-speed serial data. In conjunction with the frequency dependent load, the amplifier input section amplifies and equalizes the high-speed serial data to produce an amplified and equalized serial data.

Abstract: A device and a method for processing high data rate serial data includes a VCO initial frequency calibration circuit. The circuit includes a frequency detection block for indicating a difference between a reference clock and a divided VCO clock, a frequency calibration block that produces a digital output signal based upon the difference between the reference clock and the divided VCO clock, and a digital-to-analog converter for producing an analog VCO adjust signal. The frequency detection block produces a plurality of signals based upon the reference clock and the divided VCO clock. A plurality of user selected inputs selects a frequency detection lock range and hysteresis range and a coarse loop open calibration lock and hysteresis range. The frequency calibration block implements a state machine for producing the digital output signal that sets the initial operating frequency then adjusts the frequency of the VCO clock.

Abstract: A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element and an output sequential element. The method continues by providing a test input to the programmed circuit. The method continues by triggering the input sequential element to temporarily store the test input based on a first edge of the test clock. The method continues by triggering the output sequential element to temporarily store a test output of the programmed circuit based on a second edge of the test clock. The method continues by capturing the test output of the programmed circuit in accordance with the second edge of the test clock.

Abstract: Framing transmit encoded output data begins by determining a scrambling remainder between scrambling of an input code word in accordance with a 1st scrambling protocol and the scrambling of the input code word in accordance with an adjustable scrambling protocol. The processing continues by adjusting the adjustable scrambling protocol based on the scrambling remainder to produce an adjusted scrambling protocol. The processing then continues by scrambling the input code word in accordance with the 1st scrambling protocol to produce a 1st scrambled code word. The processing continues by scrambling the input code word in accordance with the adjusted scrambling protocol to produce a scrambled partial code word. The processing continues by determining a portion of the 1st scrambled code word based on the scrambling remainder. The process then continues by combining the scrambled partial code word with the portion of the 1st scrambled code word to produce the transmit encoded output data.

Abstract: A communication system includes a transmitter, a communication channel, and a receiver. The transmitter includes a pre-emphasis module, a summing module, a line driver, and a decision feedback pre-emphasis (DFP) module to produce a pre-emphasized serial stream of data based on a communications channel response and an inter-symbol interference level. The receiver includes a linear equalizer, a summing module, a decision module, and a decision feedback equalization (DFE) module. The linear equalizer produces an equalized serial stream of data. The summing module sums at least one data element of the equalized serial stream of data with DFE data elements to produce equalized data elements. The decision module interprets the equalized data elements to produce interpreted data elements to DFE module, which produces the DFE data elements from the interpreted data elements.

Abstract: A data alignment and deskewing module includes a delay calibration unit, a data alignment and deskew unit, and a delay unit. The delay calibration unit is operably coupled to generate a reference signal based on a reference clock and a mirrored delay line output signal. The data alignment and deskew unit is operably coupled to determine a delay selection signal based on a delayed and deskewed representation of an input data stream and propagation delay of a line on which the input data stream is received. The delay unit is operably coupled to produce the delayed and deskewed representation of the input data stream based on the reference signal and the delay selection signal.

Abstract: An integrated circuit includes a substrate, a noise sensitive circuit, and a first low impedance guard ring. The substrate includes a well-doped blocking ring that at least partially surrounds the noise sensitive circuit. The noise sensitive circuit is fabricated on the substrate. The first low impedance guard ring is fabricated on the substrate to at least partially surround the well-doped blocking ring, wherein the first low impedance guard ring is operably coupled to a first circuit ground, wherein impedance of the first low impedance guard ring is substantially less than impedance of the well-doped blocking ring.

Abstract: A receiver that includes: an oversampling module that converts a serial stream of data into a plurality of streams of oversampled data based on the receive clock; a transition location module that determines transition locations of the streams of oversampled data and the receive clock; a pointer adjust module that determines a pointer variable based on the transition locations and the receive clock; a data selection module that determines an equivalent data value for the streams of oversampled data based on the pointer variable; a staging register module that produces an offset data word and an extra data word from the equivalent data value for the oversampled data streams; and a output register module that produces a parallel data output from at least one of the offset data word and the extra data word.

Abstract: A method and apparatus for a transmitting entity within a micro-area network to establish a data transmission within the network includes processing that begins by determining the identity of a target entity within the micro-area network. The processing then continues by determining transmission characteristics of at least one communication path between the transmitting entity and target entity of the micro-area network. The processing then continues by determining a transmission convention based on the transmission characteristics. The processing then continues by providing the transmission convention to the target entity.

Abstract: A clock and data recovery circuit includes even and odd latches, a detection module, a clock recovery module, a compensating module, and a data recovery module. The even and odd latches are operably coupled to latch even and odd bits of a digital stream of data based on a recovered clock to produce even and odd latched bits. The detection module is operably coupled to produce a phase representative pulse stream based on the even and odd latched bits. The clock recovery module is operably coupled to produce the recovered clock based on the phase representative pulse stream. The compensating module is operably coupled to adjust biasing of the even and odd latches based on operating parameter changes of the clock and data recovery circuit. The data recovery module is operably coupled to produce recovered data from the even and odd latched bits based on the recovered clock.

Abstract: A programmable differential signaling system includes a programmable bias generator and a plurality of input/output modules. The programmable bias generator is operably coupled to generate a first global bias signal and a second global signal based on desired signal properties of one of a plurality of differential signaling conventions. The a plurality of input/output modules is operably coupled to convert between differential signaling and single ended signaling, wherein actual signal properties of the differential signaling are regulated based on the first and second global bias signals to substantially equal the desired signal properties.

Abstract: The present invention includes an apparatus and method to optimize a set of test designs to obtain complete coverage while reducing bit stream size for programmable fabric. Test designs are selected that do not result in lost coverage. The method selects a set of test designs, removes the set of test designs, and then determines if coverage is lost. If coverage is lost, the method creates a new set of test designs to test the lost coverage. If the new set of test designs is smaller than the removed set, the new set of test designs is added to the test design suite; otherwise the removed test designs are added back to the test design suite. The decision to add the new test designs or removed test designs is based on a number of criteria including evaluating the number of uniquely tested resources in each test design.

Abstract: An analog front-end having built-in equalization includes a control module and a tunable gain stage. The control module is operably coupled to provide a frequency response setting based on a channel response of a channel providing high-speed serial data to the analog front-end. The tunable gain stage includes a frequency dependent load and an amplifier input section. The frequency dependent load is adjusted based on the frequency response setting. The amplifier input section is operably coupled to the frequency dependent load and receives the high-speed serial data. In conjunction with the frequency dependent load, the amplifier input section amplifies and equalizes the high-speed serial data to produce an amplified and equalized serial data.

Abstract: The present invention includes a method and an apparatus, in one embodiment, in the form of an integrated circuit and programmable fabric design tool, for calculating skew in a manner that does not include unnecessary skew values, resulting in a skew value without pessimism. A setup slack determination ensures that data launched or transmitted from a source register reaches the destination register within a specified maximum cycle time and is defined as the difference between a minimum (early) destination time and a maximum (late) source time without unnecessary skew values. A hold check slack determination ensures the data does not “race” from the source register to the destination register on the same clock edge and is calculated as a difference between a maximum (late) destination time and a minimum (early) source time without unnecessary skew values. A circuit's operational frequency and layout are based upon the method for calculating skew.

Abstract: The present invention includes a method and an apparatus, in one embodiment, in the form of an integrated circuit and programmable fabric design tool, for calculating skew in a manner that does not include unnecessary skew values, resulting in a skew value without pessimism. A setup slack determination ensures that data launched or transmitted from a source register reaches the destination register within a specified maximum cycle time and is defined as the difference between a minimum (early) destination time and a maximum (late) source time without unnecessary skew values. A hold check slack determination ensures the data does not “race” from the source register to the destination register on the same clock edge and is calculated as a difference between a maximum (late) destination time and a minimum (early) source time without unnecessary skew values. A circuit's operational frequency and layout are based upon the method for calculating skew.

Abstract: A signal detection circuit includes a first signal multiplier operably coupled to square an input signal, a second signal multiplier operably coupled to square a reference signal, and a filter module operably coupled to produce a digital output representative of the input signal based on a squared input signal and a squared reference signal.

Abstract: A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element and an output sequential element. The method continues by providing a test input to the programmed circuit. The method continues by triggering the input sequential element to temporarily store the test input based on a first edge of the test clock. The method continues by triggering the output sequential element to temporarily store a test output of the programmed circuit based on a second edge of the test clock. The method continues by capturing the test output of the programmed circuit in accordance with the second edge of the test clock.

Abstract: A high speed transceiver operable to receive lower data rate transmissions includes an oversampling module and a data recovery system. The oversampling module is operably coupled to oversample a unique alignment sequence and data of a data stream received at a first data transmission to produce an oversampled unique alignment sequence and oversampled data, respectively, wherein the first data transmission rate is less than a serial bit rate of the high speed transceiver.

Abstract: A high speed transceiver operable to receive lower data rate transmissions includes an oversampling module, an aligning module, a selecting module, and a memory module. The oversampling module is operably coupled to oversample an n-bit data word at an oversampling rate of m to produce an m by n bit oversampled data word, wherein the n-bit data word is received at a first data transmission rate that is less than a serial bit rate of the high speed transceiver. The transition boundary module is operably coupled to determine transition boundary data of the m by n bit oversampled data word in accordance with a clock of the high speed transceiver to produce transition boundary data. The selecting module is operably coupled to select representative bits in accordance with the transition boundary data to produce a recovered data word. The memory module is operably coupled to store the recovered data word.