Abstract: A method and apparatus for frequency shift-keying (FSK) demodulation includes processing that begins by generating a charge signal, a data acquisition signal, and a reset signal from an I component and a Q component of an FSK modulated signal. The processing continues by generating a delta frequency signal based on the charge signal, the data acquisition signal, and the reset signal. The delta frequency signal is representative of the frequency difference used within the FSK modulation to indicate a logic 1 and a logic 0. The processing then continues by demodulating the delta frequency signal to recapture a stream of data.

Abstract: A non-power-of-two modulo N Gray-code counter (the “Gray-code counter”) and a binary incrementer-decrementer algorithm are disclosed.

Abstract: An on-chip differential multi-layer inductor includes a 1st partial winding on a 1st layer, a 2nd partial winding on the 1st layer, a 3rd partial winding on a 2nd layer, a 4th partial winding on the 2nd layer, and an interconnecting structure. The 1st and 2nd partial windings on the 1st layer are operably coupled to receive a differential input signal. The 3rd and 4th partial windings on the 2nd layer are each operably coupled to a center tap. The interconnecting structure couples the 1st, 2nd, 3rd and 4th partial windings such that the 1st and 3rd partial windings form a winding that is symmetrical about the center tap with a winding formed by the 2nd and 4th partial windings. By designing the on-chip differential multi-layer inductor to have a desired inductance value, a desired Q factor, and a desired operating rate, a desired resonant frequency and corresponding desired capacitance value can be determined.

Abstract: A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, complimentary transistor, current cource, a 1st load, and a 2nd load. The 1st input transistor is operably coupled to receive a 1st input logic signal, which may be one phase of a first differential input signal. The 2nd input transistor is coupled in parallel with the 1st input transistor and is further coupled to receive a 2nd input logic signal, which may be one phase of a 2nd differential input signal. The complimentary transistor is operably coupled to the sources of the 1st and 2nd input transistors and to receive a complimentary input signal, which mimics the other phase of the 1st differential logic signal and the 2nd differential logic signal. The current source sinks a fixed current from the 1st and 2nd input transistors and the complimentary transistor.

Abstract: A configurable multi-port modem includes a plurality of hybrids, a plurality of receivers, a plurality of transmitters, and a switching module. Each of the plurality of hybrids is operably coupled to provide 2 to 4 wire coupling for a corresponding one of a plurality of twisted pairs that are coupled to the configurable multi-port modem. Each of the plurality of receivers is operably coupled to convert inbound DSL signals into inbound data. Each of the plurality of transmitters is operably coupled to convert outbound data into outbound DSL signals. The switching module is operable to couple at least one of the plurality of hybrids to at least one of the plurality of receivers and to at least one of the plurality of transmitters based on a configuration control signal.

Abstract: An edge sensitive detection circuit includes a filter module and a soft latch module. The filter module is operably coupled to receive an input logic signal that corresponds to the triggering of an event and produces a pulse signal in response to an edge of the input logic signal. The filter may include a capacitor operably coupled to a controlled impedance, an inverter and a driver transistor, wherein the capacitor senses an edge of the input logic signal and, in combination with the controlled impedance, produces the pulse signal. The soft latch module is operably coupled to receive the pulse signal and to latch a logic value in accordance with the pulse signal.

Abstract: A printed antenna includes a 1st dipole section and a 2nd dipole section. The 1st dipole section includes a 1st radiation section and a 1st frequency section. The 2nd dipole antenna section includes a 2nd radiation section and a 2nd frequency section. The 1st and 2nd dipole antenna sections are electrically coupled together such that the currents flowing through the 1st and 2nd frequency sections substantially cancel and the current flowing through the 1st and 2nd radiation sections are substantially cumulative for a ½ wavelength antenna. For a full wavelength antenna, 1st and 2nd dipole antenna sections are electrically coupled together such that the currents flowing through the 1st and 2nd frequency sections are substantially cumulative and the current flowing through the 1st and 2nd radiation sections substantially cancel.

Abstract: An integrated circuit includes electrical components that include one or more electrical elements on one or more dielectric layers. The electrical element has a geometric shape that exceeds prescribed integrated circuit manufacturing limits in at least one dimension. To achieve compliance with foundry rules, the electrical element is fabricated to include a non-conducting region that negligibly effects the electrical characteristics. The non-conducting region includes a hole, a series of holes, a slot and/or a series of slots spaced within the electrical element at dimensions that are less than the integrated circuit manufacturing limits.

Abstract: An on-chip multiple tap transformed balun includes a 1st winding and a 2nd winding having two portions. The 1st winding is on a 1st layer of an integrated circuit and is operably coupled for a single ended signal. The 1st and 2nd portions of the 2nd winding are on a 2nd layer of the integrated circuit. The 1st portion of the 2nd winding includes a 1st node, a 2nd node, and a tap. The 1st node is operably coupled to receive a 1st leg of a 1st differential signal and the 2nd node is coupled to a reference potential. The tap of the 1st portion is operably coupled for a 1st leg of a 2nd differential signal. The 2nd portion of the 2nd winding includes a 1st node, 2nd node, and tap. The 1st node is operably coupled to receive a 2nd leg of the 1st differential signal and the 2nd node is operably coupled to the reference potential. The tap of the 2nd portion is coupled for a 2nd leg of the 2nd differential signal.

Abstract: A differential latch includes a sample transistor section, a hold transistor section, a 1st gating circuit and a 2nd gating circuit. The sample transistor section is operably coupled to sample, when coupled to a supply voltage (e.g., VDD and VSS) a differential input signal. The hold transistor section is operably coupled to latch, when coupled to the supply voltage, the sampled differential input to produce a latched differential signal. The 1st gating circuit is operable to couple the sampled transistor section to the supply voltage in accordance with a 1st clocking logic operation and a 2nd clocking logic operation. The 2nd gating circuit is operable to couple the hold transistor section to the supply voltage in accordance with a 3rd clocking logic operation and a 4th clocking logic operation.

Abstract: A method and apparatus for producing multiple clock signals having controlled duty cycles and phase relationships includes processing that begins by generating a plurality of delayed clock signals from an input clock signal based on a delay control signal. The processing then continues by producing a first multiple clock signal from a first set of a plurality of delayed clock signals and the input clock signal. The processing then continues by producing a second multiplied clock signal from a second set of the plurality of delayed clock signals, where the second multiplied clock signal is delayed from the first multiplied clock signal in accordance with a delay of at least one of the delayed clock signals. The processing then continues by generating the delayed control signal based on the first multiplied clock signal, where the delay control signal controls delays of the plurality of delayed clock signals.

Abstract: A high speed data communication system includes a receiver to recover data and clock signals from communicated data. The receiver circuit has a dual phase lock loop (PLL) circuit. A fine loop of the PLL includes a phase detector providing a differential analog voltage output. Transconductance circuitry converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a high impedance output, a small transconductance value and can provide variable gain control. A coarse loop of the PLL allows for frequency acquisition of an internal oscillator.

Abstract: A method and apparatus for modulating a signal into a digital representation thereof includes processing that begins by integrating a difference between an input signal and an analog feedback signal to produce an integrated signal. The processing then continues by quantizing the integrated signal to produce a quantized signal. The processing continues by generating a spectral shaping signal to compensate for non-linearities of the analog feedback signal. The processing further continues by injecting the spectral shaping signal into the quantized signal to produce a spectrally adjusted quantized signal. The processing further continues by converting the spectrally adjusted quantized signal into the analog feedback signal.

Abstract: A method and apparatus for enabling a stand-alone integrated circuit (IC) includes processing that begins by establishing an idle state that holds at least a portion of the stand-alone integrated circuit in a reset condition when a power source is operably coupled to the stand-alone integrated circuit. A stand-alone integrated circuit includes generally an on-chip power converter, a reset circuit and some functional circuitry, which may be a microprocessor, digital signal processor digital circuitry, state machine, logic circuitry, analog circuitry, and/or any type of components and/or circuits that perform a desired electrical function. When a power enable signal is received, the on-chip power converter is enabled to generate at least 1 supply from the power source. The processing continues by enabling functionality of the stand-alone integrated circuit when the at least one supply has substantially reached a steady state condition.

Abstract: A stereo separation circuit includes a pair of amplifiers and a pair of divider circuits. Each of the amplifiers is coupled to receive a stereo signal (e.g., a left stereo signal or a right stereo signal) and the output of the other amplifier through a portion of one of the divider circuits. The other portion of the divider circuit is coupled as feedback across an amplifier. A ratio between the feedback portion of the divider circuit and the other portion of the divider circuit provides a separation ratio. The greater the separation ratio, the greater the perceived audio separation of the stereo signals.

Abstract: A method and apparatus for sample rate conversion in an analog to digital converter. Such a method and apparatus include processing that begins by receiving an input digital stream at a first clock rate from an oversampling quantizer (e.g., a sigma delta modulator). The processing continues by integrating the input digital stream over multiple clock cycles at the first clock rate to produce an integrated digital signal. The processing continues by determining when an interpolated digital value of the integrated digital signal is to be passed to a differentiation stage based on a difference between a sample rate conversion value and a reference value. The processing continues by, when the difference is within a targeted range (e.g.

Abstract: A method and apparatus for frequency shift-keying (FSK) demodulation includes processing that begins by generating a charge signal, a data acquisition signal, and a reset signal from an I component and a Q component of an FSK modulated signal. The processing continues by generating a delta frequency signal based on the charge signal, the data acquisition signal, and the reset signal. The delta frequency signal is representative of the frequency difference used within the FSK modulation to indicate a logic 1 and a logic 0. The processing then continues by demodulating the delta frequency signal to recapture a stream of data.

Abstract: A method and apparatus for analog to digital conversion includes processing that begins by quantizing an analog input signal to produce a stream of digital data at an over sampling rate. The processing continues by producing partially filtered data based on a moving sum of the stream of data. The processing continues by decimation filtering the partially filtered data to produce a digital output value.

Abstract: A method and apparatus for generating a fast multiply accumulation circuit includes processing that begins by determining number of current partial products for a multiplication of a first multiplicand and a second multiplicand. The processing then continues by determining size of the current partial products. The processing then continues by identifying one of a plurality of reduction patterns based on the size of the current partial products. The processing then continues by determining number of, and configuration of, full adders and half adders required for a reduction function of the current partial products based on the one of the plurality of reduction patterns and the size of the current partial products, wherein the multiply-accumulator performs the reduction function.

Abstract: A phase lock loop includes a phase detector, a charge pump circuit, a controlled oscillator, and a jitter control circuit. The control oscillator may also include a biasing circuit to provide the frequency biasing. The phase detection circuit is operably coupled to receive the reference signal and a feedback signal and to produce therefrom a phase different signal. The phase different signal is provided to the charge pump circuit, which includes a first current source and a second current source. The first current source is dominate when the phase different signal is in a first stage (e.g., charge up) and the second current source is dominate when the phase signal is in the second state (e.g., charge down). The charge pump circuit outputs a representative signal that is provided to the control oscillator which, in response, generates the output signal. The output signal is fed back to the phase detection circuit as the feedback signal.