Patents Represented by Attorney Townsend and Townsend & Crew, LLP
  • Patent number: 7840766
    Abstract: A storage system for writing data sent from a computer to storage regions is described. The storage system includes storage regions configured to store data, and a controller coupled with the storage regions. The controller is configured to control writing of the data from the computer. The controller is further configured to set a first storage region for writing data sent from the computer to a second storage region. The controller then acquires a snapshot of the first storage region at a predetermined time, writes a snapshot journal for the snapshot to the second storage region, and manages a snapshot management table. The controller also acquires a recovery point journal when a recovery volume designated by the computer is made, and writes the recovery point journal to the second storage region.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: November 23, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiaki Eguchi, Hiroshi Arakawa
  • Patent number: 7838364
    Abstract: A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: November 23, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Soo Kim, Hong-Seon Yang, Se-Aug Jang, Seung-Ho Pyi, Kwon Hong, Heung-Jae Cho, Kwan-Yong Lim, Min-Gyu Sung, Seung-Ryong Lee, Tae-Yoon Kim
  • Patent number: 7839692
    Abstract: A soft program method in a non-volatile memory device for performing a soft program step so as to improve threshold voltage distribution of an erased cell is disclosed. The soft program method in a non-volatile memory device includes performing a soft program for increasing threshold voltages of memory cells by a given level, wherein an erase operation is performed about the memory cells, performing a verifying operation for verifying whether or not a cell programmed to a voltage more than a verifying voltage is existed in each of cell strings, and performing repeatedly the soft program until it is verified that whole cell strings have one or more cell programmed to the voltage more than the verifying voltage.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: November 23, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seong Je Park
  • Patent number: 7838361
    Abstract: A method for fabricating a recess gate in a semiconductor device includes etching a silicon substrate to form a trench that defines an active region, forming a device isolation layer that gap-fills the trench, forming a hard mask layer over the silicon substrate, the hard mask layer comprising a stack of an oxide layer and an amorphous carbon layer, wherein the hard mask layer exposes a channel target region of the active region, and forming a recess region with a dual profile by first etching and second etching the channel target region using the hard mask layer as an etch barrier, wherein the second etching is performed after removing the amorphous carbon layer.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: November 23, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Tae Cho, Eun-Mi Kim
  • Patent number: 7837357
    Abstract: An illumination system has a light source, an optical train, and a wavelength beam splitter. The optical train focuses light from the light source into a defined geometrical pattern on a surface. The wavelength beam splitter transmits light of a first wavelength and redirects light of a second wavelength. One of these wavelengths is included by the light from the light source, while the other is an emission wavelength generated by thermal excitation of the surface by the focused geometrical pattern.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: November 23, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Dean C. Jennings, Timothy N. Thomas
  • Patent number: 7840874
    Abstract: A cache tag comparison unit in a cache controller evaluates tag data and error correction codes to determine if there is a cache hit or miss. The cache tag comparison unit speculatively compares the tag data with the request tag without regard to error correction. The error correction code verifies whether this initial comparison is correct and provides a confirmed cache hit or miss signal. The tag data is compared with the request tag to determine a provisional cache hit or miss, and in parallel, the error correction code is evaluated. If the error code evaluation indicates errors in the tag data, a provisional cache hit is converted into a cache miss if errors are responsible for a false match. If the error code evaluation identifies the locations of errors, a provisional cache miss is converted into a cache hit if the errors are responsible for the mismatch.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: November 23, 2010
    Assignee: MIPS Technologies, Inc.
    Inventor: Rojit Jacob
  • Patent number: 7840835
    Abstract: In a network computer system, recovery may be impossible from a fault when the fault occurs in a network switch in a network or a device such as an external disk device. Provided is a computer system that includes a plurality of servers, a plurality of network, a plurality of external disk devices, and a management computer, in which the management computer detects a fault which is occurred, retrieves an application stop server inaccessible to the used disk due to the fault, retrieves the disk for storing the same contents as contents stored in the disk used by the retrieved application stop server and the external disk device including the disk, retrieves an application resuming server capable of accessing the retrieved external disk device, and transmits an instruction to boot by using the retrieved disk to the retrieved application resuming server.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: November 23, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Keisuke Hatasaki, Takao Nakajima
  • Patent number: 7839781
    Abstract: A method for configuring service curves for managing the output port of a networking device includes the following steps. A multitude of traffic classes is defined, each traffic class being characterized by a bandwidth and a delay priority. A multitude of traffic service curves is computed, each of the plurality of traffic service curves is associated with a different one of the multitude of traffic classes. At least one of the multitude of traffic classes service curves is characterized by a shifted two-piece linear function shifted such that the service curve limits service to during a nonzero time period prior to the start of the two-piece linear function.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: November 23, 2010
    Assignee: Riverbed Technology, Inc.
    Inventors: Lap Nathan Trac, Steven McCanne
  • Patent number: 7838726
    Abstract: The invention provides methods of introducing heterologous cells into fish. After introduction cells remain viable, and in some instances proliferate, for sufficient time to conduct a variety of analyses on the heterologous cells or the fish or both. Such methods are useful for screening potential drugs for toxicity toward introduced cells or for capacity to stimulate differentiation and/or proliferation of introduced cells. Such methods are also useful for diagnosing the presence of small quantities of cancerous cells or pathogens in patient tissue samples. Such methods are also useful for culturing cells for subsequent use in cell or tissue engineering.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: November 23, 2010
    Assignee: Phylonix Pharmaceuticals, Inc.
    Inventors: George N Serbedzija, Patricia McGrath
  • Patent number: 7839728
    Abstract: A technique for investigating differences of composition and structural state of a recording layer of an optical disc along with other defects, such as scratches, contamination, warp and distortion, prior to video recording and for setting up appropriate recording conditions in compliance with this result to thereby perform recording is disclosed. In an optical disc recording device capable of recording information on an optical disc, a region to be investigated is defined based on the video recording reservation contents. Then, investigate and evaluate the disc state which can affect the recording quality in a target disc region to be recorded. Next, based on investigation/evaluation results, perform recording setup, recording speed setup, servo control setup and recording position setup to thereby perform the recording. By appropriately modifying the recording setup on a case-by-case basis, it is possible to achieve high-quality recording.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: November 23, 2010
    Assignees: Hitachi, Ltd., Hitachi-LG Data Storage, Inc.
    Inventor: Akio Fukushima
  • Patent number: 7838253
    Abstract: The present invention relates to regulation of cold sensation and pain. More particularly, the present invention is directed to nucleic acids encoding a member of the transient regulatory protein family, CMR1, which is involved in modulation of the perception of cold sensations and pain. The invention further relates to methods for identifying and using agents that modulate cold responses and pain responses stimulated by cold via modulation of CMR1 and CMR1-related signal transduction.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: November 23, 2010
    Assignee: The Regents of the University of California
    Inventors: David Julius, David D. McKemy, Werner M. Neuhausser
  • Patent number: 7839653
    Abstract: A backplane has signal connectors for connecting signals of logical boards connected to an upper level of the backplane; signal connectors for connecting signals of logical boards connected to a lower level of the backplane; power source connectors for supplying power to the logical boards connected to the upper level of the backplane; and power source connectors for supplying power to the logical boards connected to the lower level of the backplane. Some power source connectors are formed at one end of the backplane and the other power source connectors are formed at the other end of the backplane.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: November 23, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Koga, Mitsuru Inoue
  • Patent number: 7836893
    Abstract: Systems and methods provide for stabilizing the amount of laser energy delivered to a target from a laser device. Generally, delivered laser energy is measured over multiple laser pulses or over time in the case of a constant wave laser. A decrease is then calculated in the delivered energy, the decrease being caused by accumulation of one or more substances, such as ozone, along the laser beam delivery path due to passage of the laser beam along the path. Using this calculated decrease, a laser device may be adjusted to compensate for the decrease in delivered energy due to the accumulated substance(s), thus stabilizing the amount of energy delivered to the target.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: November 23, 2010
    Assignee: AMO Manufacturing USA, LLC
    Inventor: Keith Holliday
  • Patent number: 7837476
    Abstract: A socket assembly formed of hollow tubes for connecting an array of terminals off opposing electronic structures with both axial and lateral resilience, wherein the resilience is achieved through angular cuts in the tubes.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: November 23, 2010
    Assignee: Centipede Systems, Inc.
    Inventor: Thomas H. Di Stefano
  • Patent number: 7837691
    Abstract: A device for performing a surgical procedure on a knee comprises a femoral assembly comprising a stationary femoral member attachable to the distal femur, an adjustable femoral member movably coupled with the stationary member to adjust tension in at least one ligament of or adjacent the knee and an adjustment mechanism coupled to the assembly. The adjustable member includes at least one positioning feature that moves relative to the distal femur as the adjustable member is adjusted and identifies at least one position on the distal femur. The adjustable member is movably couplable with a tibial member engaged with a proximal tibia to allow the knee to be moved through a range of motion without removing the femoral and tibial members. The mechanism includes an actuator positioned proximate a medial or lateral portion of the adjustable member. The actuator is configured to adjust an opposite portion of the adjustable member.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: November 23, 2010
    Assignee: Synvasive Technology, Inc.
    Inventors: Kevin Cordes, Michael G. Fisher
  • Patent number: 7834710
    Abstract: An oscillator circuit includes a first terminal, a second terminal, a resonator that is connected to the first terminal and the second terminal, a first capacitor that is connected to the first terminal and a ground line supplying the ground electric potential, a second capacitor that is connected to the second terminal and the ground line, m inverters, where m is an odd number equal to or larger than three, which are connected in series between the first terminal and the second terminal, and a third capacitor that is connected to an input terminal of the n-th (where n is an integer satisfying 1?n<m) inverter, counted from an input side of the inverter array and an output terminal of the (n+1)-th inverter.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: November 16, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Aritsugu Yajima
  • Patent number: 7836318
    Abstract: Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: November 16, 2010
    Assignee: NVIDIA Corporation
    Inventors: Jonah M. Alben, Sean Jeffrey Treichler, Adam E. Levinthal
  • Patent number: D627618
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: November 23, 2010
    Assignee: Buck Knives, Inc.
    Inventors: James MacNair, Eric P. Linn
  • Patent number: D627771
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: November 23, 2010
    Assignee: At Hand Gear, LLC
    Inventors: Christopher A. Smith, Carm Pierce, Mysore Y. Jaisimha, David Herbig
  • Patent number: D627918
    Type: Grant
    Filed: February 6, 2010
    Date of Patent: November 23, 2010
    Assignee: Topanga Technologies, Inc.
    Inventors: Frederick M. Espiau, Mehran Matloubian