Abstract: Systems and methods are disclosed to insulate a vessel includes placing a plurality of shells on all sides of the vessel without providing a direct energy pathway from outer walls of the vessel to the inner walls of the vessel; placing the shells under a vacuum; cryogenically cooling the shells to a cryogenic temperature; and while under vacuum, allowing the shell temperature to rise from the cryogenic temperature to ambient temperature.
Abstract: A three dimensional semiconductor device, comprising: a plurality of circuit blocks including programmable logic blocks having predetermined positions within the device; a plurality of pads having predetermined positions within the device; and a configuration memory circuit coupled to the programmable logic blocks having a plurality of fabricating methods without altering the predetermined positions of the pads and the circuit blocks.
Abstract: A programmable logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. In a multiplier configuration, the circuit comprises a logic block; and a latch having a latch output coupled to a logic block input, wherein the latch output computes an AND function of a first and second latch input.
Abstract: A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.
Abstract: A time multiplexed programmable switch of a semiconductor device comprising: a first node; and a plurality of second nodes, each of the second nodes having a path to couple to the first node, the path comprising: a first configurable device configured to select or deselect the path; and a second configurable device in series with the first configurable device configured to select or deselect the path by a digital signal; wherein, the plurality of digital signals are time multiplexed to have no more than one second device in the select state within a time interval.
Abstract: A semiconductor device, wherein: a first fabricating option provides a plurality of user configurations to configure the device functionality; and a second fabricating option hard-wires a said functional configuration, the second option comprising a plurality of common masks and fewer processing steps compared to the first option.
Abstract: Systems and methods are disclosed to operate a mobile device. The system includes a message center; an engine coupled to the message center; and a mobile device wirelessly coupled to the message center, wherein the engine specifies one or more meeting locations and wherein at least one meeting location comprises a location designated by an advertiser.
Abstract: A monitoring system includes one or more wireless nodes forming a wireless mesh network; a user activity sensor including a wireless mesh transceiver adapted to communicate with the one or more wireless nodes using the wireless mesh network; and a digital monitoring agent coupled to the wireless transceiver through the wireless mesh network to request assistance from a third party based on the user activity sensor.
Abstract: Systems and methods are disclosed to analyze a patent document by receiving patent application text including background, description of drawings, description and claims; generating a claim chart showing claim dependencies; checking for antecedent, support in drawings, support in the description; generating a navigable claim hierarchy; and generating a diagnostic message for the patent document.
Abstract: Systems and methods are disclosed for reducing the cost of sending messages over an intermittent network of computing devices via multiple communication channels by creating a first message on a first device, the message intended to be sent to a second device over the network multiple communication channels; applying a first policy to reduce the cost of sending messages over the intermittent network of computing devices, the first policy containing one or more rules to determine whether to send the first message to the second device, each rule being a function of one or more messaging attributes of messages, channels or the system environment; and dynamically updating the first policy by sending a second message to the first device, the second message being a system message that results in the addition, deletion or other modification of the rules contained in the policy to reduce the cost of sending messages over the intermittent network of computing devices.
Abstract: Systems and methods are disclosed for sending a code from a mesh network key and wirelessly communicating the code with one or more mesh network appliances over a mesh network such as ZigBee; receiving the code over the mesh network by a mesh network lock controller; and providing access to the secured area upon authenticating the code.
Abstract: A programmable interconnect structure for an integrated circuit comprises: a pass-gate fabricated on a substrate layer to electrically connect a first node to a second node; and a configuration circuit including at least one memory element to control said pass-gate fabricated substantially above said substrate layer; and a programmable method to select between isolating said first and second nodes and connecting said first and second nodes. A programmable buffer structure for an integrated circuit comprises: a first and a second terminal; and a programmable pull-up and a programmable pull-down circuit coupled between said first and second terminals; and a configuration circuit including at least one memory element coupled to said pull-up and pull-down circuits; and a programmable method to select between isolating said first terminal from second terminal by deactivating said pull-up and pull-down circuits, and coupling said first terminal to second terminal by activating said pull-up and pull-down circuits.
Abstract: A smaller mask programmable gate array (MPGA) device derived from a larger field programmable gate array (FPGA), comprising: a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the FPGA; and input/output pads matching a subset of the input/output pads of the FPGA; wherein, a design that is mapped to said smaller region of the FPGA device using said subset of input/output pads by a user programmable means can be identically mapped to the MPGA by a hard-wire circuit. Such a gate array further comprises a mask programmable metal-circuit in lieu of a user programmable configuration circuit of the FPGA; and a logic block to input/output pad connection in lieu of a logic block to a register at the boundary of said smaller region to an input/output pad connection of the FPGA.
Type:
Grant
Filed:
March 1, 2007
Date of Patent:
March 2, 2010
Assignee:
Tier Logic, Inc.
Inventors:
Raminda Udaya Madurawe, Peter Ramyalal Suaris, Thomas Henry White
Abstract: An apparatus includes a plurality of wash durable clothing strands; an array of nano electronic elements fabricated in the strands; and an array of memory elements coupled to the nano electronic elements. The nano electronic elements can include solar cells, display elements, or antennas, among others.