Abstract: An integrated power amplifier (PA) module formed on a substrate includes a first cluster of transistor cells positioned in a first portion of the substrate; a second cluster of transistor cells positioned in a second portion of the substrate and spaced apart from the first portion; and a combiner coupled to the first and second clusters to combine the output of the first and second clusters.

Abstract: A configurable look up table (LUT) structure of an integrated circuit comprising: a first, a second and a third intermediate LUT stage, each of the LUT stages comprising one or more inputs and an output, wherein: the output of first intermediate LUT stage is coupled to an input of the second and third intermediate LUT stages; and the second intermediate LUT stage generates an arithmetic function of two bits and a carry-in signal received as inputs to the LUT structure; and the third intermediate LUT stage generates a carry-out signal.

Abstract: A semiconductor device includes a plurality of circuit blocks; and a configuration circuit coupled to the plurality of circuit blocks to program the circuit blocks, the configuration circuit comprising a plurality of memory elements, the memory elements further comprising: a first set of memory elements to store a first instruction; and a second set of memory elements to store a second instruction; and a global control signal to select the first or second instruction in the configuration circuit to program the circuit blocks.

Abstract: A programmable integrated circuit (IC), wherein: a programmable logic circuit is programmed to a user specification by configuring a transistor gate control signal generated by a read only memory (ROM) element positioned substantially above or below the transistor.

Abstract: A monitoring system includes one or more cameras to determine a three dimensional (3D) model of a person; means to detect a dangerous condition based on the 3D model; and means to generate a warning when the dangerous condition is detected.

Abstract: Systems and methods are disclosed to fabricate an electronic device on a substrate by genetically engineering first, second, third, and fourth viruses each having a plurality of selective binding sites; forming first, second, third, and fourth viral biotemplates by immersing the first, second, third, and fourth viruses in one or more solutions with nano materials coupleable to the binding sites of the viruses; self-assembling a gate with the first viral biotemplate having one site attachable to the substrate; self-assembling a source above the gate with the second viral biotemplate; self-assembling a channel with the third viral biotemplate having one site attachable to the second viral biotemplate; and self-assembling a drain with the fourth viral biotemplate having one site attachable to the third viral biotemplate.

Abstract: Systems and methods are disclosed for a wireless communications device for receiving wireless electronic signals including first wireless electronic signals at a first frequency and second wireless electronic signals at a second frequency. The wireless communications device includes an antenna adapted to convert the wireless electronic signals into input electronic signals, and an amplifier coupled to the antenna, said amplifier being capable of amplifying the input electronic signals to produce amplified electronic signals and a diplexer adapted to receive the amplified electronic signals and selectively output one of the first electronic signals at the first frequency and the second electronic signals at the second frequency.

Abstract: A package for an integrated circuit includes a chip having a plurality of nodes adapted to receive signals from or to output signals to an external circuit; and a frame having a plurality of contact points each coupled to one node of the chip and to a pad, wherein each pad comprises a nano material.

Abstract: In a first aspect, a three-dimensional semiconductor device, wherein: a configurable memory element coupled to a programmable logic circuit to program the logic circuit is positioned substantially above the logic circuit. In a second aspect, a three-dimensional semiconductor device, comprising: a first module layer having a circuit block; and a second module layer positioned substantially above the first module layer, comprising a configuration circuit coupled to the circuit block to program the circuit block.

Abstract: Timing exact design conversions from an original field programmable device to an application specific device is disclosed. In a first aspect, a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC) comprises a user configurable element in the FPGA replaced by a mask configurable element in the ASIC. In a second aspect, an FPGA design conversion to an ASIC comprises converting a user configurable memory bit pattern generated by a software tool to program the programmable content of the FPGA to a hard-wired metal pattern for the ASIC.

Abstract: A radio frequency (RF) module includes a first substrate adapted to receive passive circuits; and a second substrate adapted to receive active circuits, the first and second substrates electrically coupled through pads positioned on opposing surfaces of the first and second substrate.

Abstract: A highly economical alterable ASIC implements partitioned segments of an ASIC design in a smaller Silicon foot-print, each segment utilizing the entire IC. The device is able to switch quickly between the multiple segments with global control signals, without incurring long delays to reconfigure configuration memory. The alterable ASIC comprises programmable logic blocks and a configuration circuit with multiple sets of configuration memory, each set programmed to hold an optimized segment. Either random access memory (RAM) or mask configured read only memory (ROM) store the partitioned segments.

Abstract: A programmable look-up-table (LUT) structure adapted for carry logic incrementer implementation in an integrated circuit, comprising: three or more data inputs and a carry-in input, said data inputs comprised of consecutive bits in a data string, said carry-in comprised of the increment value to the least order bit of said data string; and three or more data outputs and a carry-out output, said data outputs comprised of the incremented values of said data inputs, and said carry-out resulting from the incremented value of the highest order bit of said data inputs; wherein, said three or more data outputs are computed in a single carry computation stage within the LUT structure.

Abstract: A programmable interconnect structure to couple a first wire segment to a second wire segment of an integrated circuit comprising: a pass-gate to electrically couple the first wire segment to the second wire segment fabricated on a substrate layer; and a configuration circuit including at least one memory element to control said pass-gate fabricated substantially above said substrate layer, wherein changing data stored in the memory element provides a programmable method to achieve one of: isolate said first wire segment from sad second wire segment; and couple said first wire segment to said second wire segment.

Abstract: Systems and methods are disclosed to process a semiconductor substrate by fabricating a first layer on the substrate using semiconductor fabrication techniques; fabricating a second layer above the first layer having one or more NANO-bonding areas; self-assemblying one or more NANO-elements; and bonding the NANO-elements to the NANO-bonding areas.

Abstract: A method of fabricating a field programmable integrated circuit comprised of: constructing a semiconductor device comprising a fuse circuit to customize the logic content of a programmable logic circuit; and attaching said semiconductor device in a detachable lid package, wherein the fuses are customized in the field by detaching the lid and blowing one or more fuse elements. The said method further comprised of: providing a custom hard-wire pattern in lieu of the fuse circuit, wherein the programmable logic circuit timing is identical between the fuse circuit and hard-wire options.

Abstract: Systems and methods for cleaning a material by applying a cleaning composition having biosurfactants and enzymes to said carpet; and bonnet cleaning the material.

Abstract: Systems and methods are disclosed for designing and tracking construction material usage by estimating volumetric properties for one or more mix designs; determining an optimum mix based on laboratory data; and field testing a sample of the optimum mix; and tracking and managing construction material usage based on the optimum mix.

Abstract: Systems and methods for cleaning a material by applying a spot cleaning composition having biosurfactants and enzymes to said carpet, wherein said spray bottle maintains lubricant inside its piston and protected from the composition.

Abstract: Systems and methods are disclosed for a frequency filtering circuit for wireless communications that includes a first resonator circuit comprising a first transmission line and a first capacitor coupled to the first transmission line and a second resonator circuit in parallel to the first resonator circuit, said second resonator circuit comprising a second transmission line and a second capacitor coupled to the second transmission line. A coupling circuit couples the first resonator circuit and the second resonator circuit.