Abstract: The present invention provides an attenuated phase shift mask (“APSM”) that, in each embodiment, includes completely transmissive regions sized and shaped to define desired semiconductor device features, slightly attenuated regions at the edges of the completely transmissive regions corresponding to isolated device features, highly attenuated regions at the edges of completely transmissive regions corresponding to closely spaced or nested device features, and completely opaque areas where it is desirable to block transmission of all radiation through the APSM. The present invention further provides methods for fabricating the APSMs according to the present invention.

Abstract: A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and/or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and/or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed.

Abstract: Dielectric rings are configured to be disposed around contact pads on a surface of a semiconductor device or another substrate. The rings may be fabricated or otherwise disposed around the contact pads of a semiconductor device or other substrate before or after conductive structures, such as solder balls, are secured to the contact pads. Upon connecting the semiconductor device face-down to a higher level substrate and establishing electrical communication between contact pads of the semiconductor device and contacts pads of the substrate, the rings prevent the material of solder balls protruding from the semiconductor device from contacting regions of the surface of the semiconductor device that surround the contact pads thereof. The rings may be preformed structures or fabricated on the surface of the semiconductor device or other substrate. For example, stereolithographic techniques may be used to form the rings.

Abstract: A method for use in the fabrication of integrated circuits is provided, which includes providing a substrate assembly having a surface. A diffusion barrier layer is formed over at least a portion of the surface. The diffusion barrier layer is formed of RuSixOy, where x and y are in the range of about 0.01 to about 10. The barrier layer may be formed by depositing RuSixOy by chemical vapor deposition, atomic layer deposition, or physical vapor deposition or the barrier layer may be formed by forming a layer of ruthenium or ruthenium oxide over a silicon-containing region and performing an anneal to form RuSixOy from the layer of ruthenium and silicon from the adjacent silicon-containing region. Capacitor electrodes, interconnects or other structures may be formed with such a diffusion barrier layer. Semiconductor structures and devices can be formed to include diffusion barrier layers formed of RuSixOy.

Abstract: Stiffeners for tapes, films, or other connective structures, which are configured to be secured to a semiconductor device component, such as a semiconductor die or substrate, by tape-automated bonding processes, are fabricated by stereolithographic processes and may include one or two or more layers. The stiffeners are configured to prevent torsional flexion or bending of the connective structure to which they are to be secured. The stiffeners may reinforce sprocket or indexing holes in connective structures. The stiffeners may include apertures through which intermediate conductive elements or other structures secured to the connective structure may be exposed or protrude. The stereolithographic method for fabricating stiffeners may include use of a machine vision system that recognizes the position and orientation of one or more connective structures on which at least an element of each of the stiffeners is to be fabricated so that the application of material thereto may be controlled.

Abstract: A semiconductor wafer saw and method of using the same for dicing semiconductor wafers including a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.

Abstract: A stacked assembly of integrated circuit semiconductor devices includes a stack of integrated circuit semiconductor devices supported by a printed circuit board (PCB). One or more multiconductor insulating assemblies provide an interface between terminals of the integrated circuit semiconductor devices and external circuitry.

Abstract: An apparatus for determining burn-in reliability from wafer level burn-in is disclosed. The apparatus according to the present invention includes nonvolatile elements on an integrated circuit for recording the number of failures at various points in time over the duration of wafer level burn-in testing. The number of failures in each IC die, along with their associated points in time, may be used to create burn-in reliability curves which are conventionally derived using other processes that may be less cost effective or not possible to effect with unpackaged IC dice. A memory device associated with the method of the present invention is also disclosed.

Abstract: A method of using adhesive tape to temporarily retain a die being temporarily held in a fixture during testing and burn-in. The method of the present invention uses a die cut piece of adhesively coated tape to hold a die in a test and burn-in fixture. Upon subsequent heating of the tape beyond the normal operating range of the adhesive coating on the tape, the die is removed from the tape, the tape is removed from the test and burn-in fixture, and the remaining adhesive, if any, is removed from the test and burn-in fixture.

Abstract: A method and apparatus for achieving a level exposed surface of a viscous material pool for applying viscous material to at least one semiconductor component by contacting at least a portion of the semiconductor component with viscous material within a reservoir. A level viscous material exposed surface is achieved by using at least one mechanism in association with the reservoir. The mechanism is configured to level the exposed surface of viscous material and maintain the exposed surface at a substantially constant level. The reservoir may be shaped such that the exposed surface of viscous material is supplied to a precise location.

Abstract: A method for making an emitter for a display device, an emitter array produced by such method, an etch mask used during such method, and a method for making such an etch mask are disclosed. The method for making the emitter comprises providing a substrate, forming a conducting layer on the substrate, forming an emitting layer on the conducting layer, forming an etch mask having a controlled distribution of a plurality of mask sizes over the emitting layer, and forming at least one emitter by removing portions of the emitting layer using the etch mask. The method for making the etch mask comprises forming an etch mask layer over an emitting layer, forming a patterning layer having a controlled distribution of mask sizes over the etch mask layer, and forming the etch mask by removing portions of the etch mask layer using the controlled distribution of mask sizes in the patterning layer.

Abstract: A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device stores a block repair configuration that determines the dimensions (e.g., the number of rows and columns spanned) of a repair block. Routing circuitry is configured by the stored block repair configuration to output some row and column address bits from received row and column addresses in a selected ratio. Comparison circuitry compares the row and column address bits output by the routing circuitry with the address of the defective cell that defines the repair block. When a match occurs, the comparison circuitry implements a block repair by activating the redundant row and by causing data to be written to or read from the activated redundant row instead of the primary array.

Abstract: A test method provides a sample of wafer level defects most likely to cause yield loss on a semiconductor wafer subdivided into a plurality of integrated circuits (ICs). Defect size and location data from an inspection tool is manipulated in an algorithm based on defect sizes and geometry parameters. The defects are classified by defect size to form size based populations. The contribution of each size range of defect population to yield loss is calculated and random samples for review are selected from each defect size population. The number of samples from each size defect population is proportional to the predicted yield impact of each sample. The method is rapid and permits on-line process modification to reduce yield losses.

Abstract: A stereolithographically fabricated, substantially hermetic package surrounds at least a portion of a semiconductor die so as to substantially hermetically seal the same. Stereolithographic processes may be used to fabricate at least a portion of the substantially hermetic package from thermoplastic glass, other types of glass, ceramics, or metals. The substantially hermetic package may be used with semiconductor device assemblies or with bare or minimally packaged semiconductor dice, including dice that have yet to be singulated from a wafer. The stereolithographic method may include use of a machine vision system including at least one camera operably associated with a computer controlling a stereolithographic application of material so that the system may recognize the position, orientation, and features of a semiconductor device assembly, semiconductor die, or other substrate on which the substantially hermetic package is to be fabricated.

Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.

Abstract: A folded interposer used to achieve a high density semiconductor package is disclosed. The folded interposer is comprised of a thin, flexible material that can be folded around one or multiple semiconductor dice in a serpentine fashion. The semiconductor dice are then attached to a substrate through electrical contacts on the interposer. The folded interposer allows multiple semiconductor dice to be efficiently stacked in a high density semiconductor package by reducing the unused or waster space between stacked semiconductor dice. Vias extending through the folded interposer provide electrical communication between the semiconductor dice and the substrate. The present invention also relates to a method of packaging semiconductor dice in a high density arrangement and a method of forming the high density semiconductor package.

Abstract: A method for forming protective layers on a plurality of semiconductor device components carried by a fabrication substrate includes applying a layer of protective material to surfaces of the semiconductor device components. The layer of protective material is then severed and the fabrication substrate is at least partially severed. Cracks and delaminated regions that are formed during severing are then healed. The protective material may be applied as a preformed sheet or in a liquid form, then at least partially cured or hardened. If a curable polymer is employed as the protective material, it may be partially cured before severing is effected, then self-healed before being fully cured. Alternatively, a thermoplastic material may be used as the protective material, with healing being effected by heating at least regions of the thermoplastic material. Semiconductor device components, including chip-scale packages, which are formed by the method are also disclosed.

Abstract: A semiconductor component configured for wafer-level testing includes a semiconductor die having at least one die contact electrically exposed for coupling with a redistribution circuit that electrically couples at least one die contact to an extended contact such as a bumped contact. The component further includes a bus conductor that traverses at least a portion of the die and electrically mates with corresponding bus conductors on other similarly prepared components on the wafer. Functional and nonfunctional dice are identified on the wafer and the nonfunctional dice are isolated from the wafer-level testing grid. Following test, dice may be subsequently tested or moved to singulation wherein the die-to-die interconnection is interrupted, allowing wafer-level tested components to be conventionally assembled.

Abstract: A stacked assembly of integrated circuit semiconductor devices includes a stack of integrated circuit semiconductor devices supported by a printed circuit board (PCB). One or more multiconductor insulating assemblies provide an interface between terminals of the integrated circuit semiconductor devices and external circuitry.

Abstract: A contact structure is provided incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor. The contact structure is fabricated by etching a contact opening through a dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening. Chemical vapor deposition of polycrystalline silicon or of a metal follows.