Patents Represented by Attorney TraskBritt, PC
  • Patent number: 7274076
    Abstract: A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at least a part of the channel region with a gate formed over the gate oxide. The gate further includes at least one implant aperture formed therein with the channel region of the substrate further including an implanted region within the channel between the source and drain regions. Methods for forming the threshold voltage adjusted transistor are also disclosed.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: September 25, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Ethan Williford
  • Patent number: 7273779
    Abstract: A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is formed along sidewalls of at least one opening in an insulating layer on a semiconductor wafer. A first conductive layer is then formed over the sacrificial liner. The sacrificial liner is then selectively removed to expose a first surface of the first conductive layer without damaging exposed components on the semiconductor wafer. Removing the sacrificial liner forms an open space adjacent to the first surface of the first conductive layer. A dielectric layer and a second conductive layer are formed in the open space, producing the double-sided capacitor. Methods of forming a double-sided capacitor having increased capacitance and a contact are also disclosed. In addition, an intermediate semiconductor device structure including at least one sacrificial structure is also disclosed.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: September 25, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Fred Fishburn, Forest Chen, John M. Drynan
  • Patent number: 7274239
    Abstract: An apparatus and method for an analog fine delay line, a hybrid delay line, and a delay locked loop (DLL) is described. In the DLL, a coarse phase detector compares a reference signal and feedback signal in controlling coarse phase adjustment signals indicating whether a delay of a coarse delay line should be increased or decreased. Similarly, a fine phase detector compares the reference signal and feedback signal to generate a locking bias signal, which may increase or decrease a delay of an analog fine delay line. The analog fine delay line and coarse delay line may be connected in series creating the hybrid delay line having a total delay comprised of the coarse delay and the fine delay. Additionally, a fine bias generator may control the fine delay in response to an initiating bias signal from an analog phase generator or the locking bias signal.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: September 25, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Feng Lin
  • Patent number: 7273684
    Abstract: A mask having transmissive elements and one or more sidelobe inhibitors for sidelobe suppression during a radiation-patterning process is provided. Sidelobe artifacts are mitigated by identifying elements as a function of the radiation wavelength for forming desired profiles on a semiconductor wafer. A diffraction rings is calculated around each of the elements to identify sidelobe interference zones and intersections of diffraction rings are located. When a guard ring around one of the intersections Sidelobe inhibitor is located at the a common sidelobe common overlap region of the guard rings. A method for forming a mask with the addition of sidelobe inhibitors as well as a method for determining the location of placement of sidelobe inhibitors is also disclosed.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: September 25, 2007
    Assignee: Micron Technology, Inc.
    Inventors: William A. Stanton, Husayn Alvarez-Gomariz
  • Patent number: 7274138
    Abstract: The disclosed method for forming a field emission display includes forming a cathode and an anode, forming a plurality of photoresist posts over the cathode, and coating the posts with a layer of coating material. The layer of coating material forms sidewalls around the posts. The photoresist posts may then be removed from within the sidewalls. The anode may then be fitted onto the sidewalls so that the sidewalls function as spacers in the field emission display.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: September 25, 2007
    Assignee: Micron Technology, Inc.
    Inventors: David A. Cathey, James J. Alwan
  • Patent number: 7274220
    Abstract: A sense amplifier for use in a memory device and in a memory-resident system. The sense amplifier operates on a lower voltage consistent with the voltage range of the differential input data and the sense amplifier further operates on a higher voltage to level-shift the output signal concurrently with the sensing operation. The sense amplifier includes a pair of differential cross-coupled inverters whose inputs are coupled to receive the data from the memory. Once the input nodes of the cross-coupled inverters are charged, the cross-coupled inverters are further coupled to pull-up and pull-down circuits that span the higher voltage range for performing the level-shifting functionality. In order to recondition the sense amplifier for a subsequent sensing process, a clamp circuit shorts the level-shifted outputs together to prevent a higher voltage level from being inadvertently passed to the memory device when isolating pass gates are reactivated.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: September 25, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Dean D. Gans
  • Patent number: 7274228
    Abstract: An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N delay taps is disclosed. Each delay tap has a delay equal to a fractional amount of the cycle delay magnitude. The method further includes delaying the clock input by an alignment magnitude to generate a first aligned phase signal and delaying each of the N delay taps by fractional amounts of the alignment magnitude to generate N phase aligned signals. A feedback loop is closed by a phase comparison between the first aligned phase signal and the cycle delay signal. The phase comparison result is used to adjust the cycle delay magnitude, which adjusts delays of the cycle delay signal and the N delay taps, and adjust the alignment magnitude, which adjusts delays of the first aligned phase signal and the N phase aligned signals.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: September 25, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Kang Yong Kim
  • Patent number: 7271096
    Abstract: A gas delivery device useful in material deposition processes executed during semiconductor device fabrication in a reaction chamber, including the gas delivery device of the present invention and a method for carrying out a material deposition process, including introducing process gas into a reaction chamber using the gas delivery device of the present invention. In each embodiment, the gas delivery device of the present invention includes a plurality of active diffusers and a plurality of gas delivery nozzles, which extend into the reaction chamber. Before entering the reaction chamber through one of the plurality of gas delivery nozzles, process gas must first pass through one of the plurality active diffusers. Each of the active diffusers is centrally controllable such that the rate at which process gas flows through each active diffuser is exactly controlled at all times throughout a given deposition process.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: September 18, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 7269042
    Abstract: A method of forming a stacked memory module from a plurality of memory devices is provided. Each of the plurality of memory devices is modified to include a logic block for decoding a plurality of chip select signals. A first high density memory module is also provided that includes the modified memory devices and a serial presence detect device. The first high density memory module is included within an electronic system. Also, an additional method of forming a stacked memory module is provided, the method requiring modification of an address buffer to include a logic block for decoding a plurality of chip select signals. A second high density memory module is also provided that includes the modified address buffer and a serial presence detect device. The second high density memory module is included within an electronic system.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: September 11, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Thomas H. Kinsley, Kevin M. Kilbuck
  • Patent number: 7268059
    Abstract: A method for securing a semiconductor device component to another element is provided. An adhesive material includes a pressure-sensitive component and a curable component is used to at least temporarily secure the semiconductor device component and the other element to each other. The pressure-sensitive component of the adhesive material temporarily secures the semiconductor device component and the other element to one another. When the semiconductor device component and the other element are properly aligned, the curable component of the adhesive material may be cured to more permanently secure them to one another. For example, when a thermoset material is used as the curable component, it may be cured by heating, such as at a temperature of lower than about 200° C. and as low as about 120° C. or less.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: September 11, 2007
    Assignee: Micron Technology, Inc.
    Inventors: W. Jeff Reeder, Tongbi Jiang
  • Patent number: 7268039
    Abstract: A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is formed along sidewalls of at least one opening in an insulating layer on a semiconductor wafer. A first conductive layer is then formed over the sacrificial liner. The sacrificial liner is then selectively removed to expose a first surface of the first conductive layer without damaging exposed components on the semiconductor wafer. Removing the sacrificial liner forms an open space adjacent to the first surface of the first conductive layer. A dielectric layer and a second conductive layer are formed in the open space, producing the double-sided capacitor. Methods of forming a double-sided capacitor having increased capacitance and a contact are also disclosed. In addition, an intermediate semiconductor device structure including at least one sacrificial structure is also disclosed.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: September 11, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Fred Fishburn, Forest Chen, John M. Drynan
  • Patent number: 7262074
    Abstract: An apparatus and method may be used for packaging a semiconductor die and a carrier substrate to substantially prevent trapped moisture therebetween and provide a robust, inflexible cost-effective bond. The semiconductor die is attached to the carrier substrate with a plurality of discrete adhesive elements so as to provide a gap or standoff therebetween. Wire bonds may then be formed between bond pads on the semiconductor die to conductive pads or terminals on the carrier substrate. With this arrangement, a dielectric filler material is disposed in the gap or standoff to form a permanent bonding agent between the semiconductor die and the carrier substrate. By applying the dielectric filler material after forming the wire bonds, the dielectric filler material coats at least a portion of the wire bonds to stabilize the wire bonds and prevent wire sweep in an encapsulation process, such as transfer molding, performed thereafter.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: August 28, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Frank L. Hall, Cary J. Baerlocher
  • Patent number: 7262488
    Abstract: A method and intermediate structure for improving the thinning and planarity of a wafer back side utilizing planarization material applied to the back side prior to at least one portion of the thinning operation and which is subsequently removed concurrently with the wafer material by one or more suitable thinning or planarization techniques. The planarization material may be applied as a thin layer or film of a hardenable material to the rough, bare back side of a wafer to produce a planar surface when hardened. The planarization material is selected to exhibit a material removal rate approximating the removal rate of the wafer material for a given removal technique such as etching, mechanical abrasion or chemical-mechanical planarization (CMP). This approach to wafer thinning and planarization results in improved process control in the form of uniform material removal rates, reduction in wafer warpage, final surface smoothness and planarity, and even distribution of residual stresses.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: August 28, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Nathan R. Draney, James M. Derderian
  • Patent number: 7259435
    Abstract: A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for example, transistors, which include a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the polysilicon/gate oxide interface and a relatively small nitrogen concentration within the gate oxide and at the gate oxide/substrate interface. Additionally, the present invention provides a method for fabricating a semiconductor device having a metal gate strap (e.g., a metal silicide layer) disposed over the polysilicon layer thereof, which device includes a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the silicide/polysilicon interface to substantially prevent cross-diffusion.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: August 21, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Zhongze Wang
  • Patent number: 7256643
    Abstract: A voltage reference generating method, source, memory device and substrate containing the same include a voltage reference generator comprised of a bandgap voltage reference circuit including a first complementary-to-absolute-temperature (CTAT) signal and a second complementary-to-absolute-temperature (CTAT) signal. The voltage reference generator further includes a differential sensing device for generating a reference signal substantially insensitive to temperature variations over an operating temperature range by differentially sensing the first and second CTAT signals. The method includes generating first and second complementary-to-absolute-temperature (CTAT) signals and generating a reference signal that is substantially insensitive to temperature variations over an operating temperature range.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: August 14, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Dong Pan, Greg A. Blodgett
  • Patent number: 7244665
    Abstract: An elevated containment structure in the shape of a wafer edge ring surrounding a surface of a semiconductor wafer is disclosed, as well as methods of forming and using such a structure. In one embodiment, a wafer edge ring is formed using a stereolithography (STL) process. In another embodiment, a wafer edge ring is formed with a spin coating apparatus provided with a wafer edge exposure (WEE) system. In further embodiments, a wafer edge ring is used to contain a liquid over a wafer active surface during a processing operation. In one embodiment, the wafer edge ring contains a liquid having a higher refractive index than air while exposing a photoresist on the wafer by immersion lithography. In another embodiment, the wafer edge ring contains a curable liquid material while forming a chip scale package (CSP) sealing layer on the wafer.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: July 17, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Peter A. Benson
  • Patent number: 7235258
    Abstract: Sustained-release compositions for delivering therapeutic concentrations of isovaleramide, isovaleric acid, and certain structurally related compounds are provided for the treatment for a variety of pathological conditions, including epilepsy and spasticity, which are ameliorated by effecting a modulation of CNS activity. The ability of the compositions to sustain relatively constant levels of the drug at a therapeutic dose in the serum for extended periods of time enables a once or twice daily administration schedule.
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: June 26, 2007
    Assignee: NPS Pharmaceuticals, Inc.
    Inventors: David S. Wells, Lian G. Rajewski, Thomas B. Marriott, James D. Pipkin, John L. Haslam
  • Patent number: 7229742
    Abstract: Methods to reduce the write time for forming mask patterns having angled and non-angled features using electron beam lithography are disclosed. In one exemplary embodiment, non-angled features of the mask pattern are formed by exposure to an electron beam. The orientation of the substrate and a path of the generally rectangular-shaped shot from the electron beam may be relatively altered such that the substrate is exposed to the electron beam to form the angled features as if they were non-angled features. In another exemplary embodiment, the electron beam lithography system determines whether it is necessary to relatively alter the orientation of the substrate and a path of the generally rectangular-shaped shot from the electron beam to form the angled features based on the number of angled features and the time required for relatively altering the orientation. Electron beam lithography systems employing a rotatable stage, rotatable apertures, or both, are also disclosed.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: June 12, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Baorui Yang
  • Patent number: 7228601
    Abstract: Various embodiments for carabiners employing a pivoting gate and having a captive eye opening are disclosed. The carabiners of the present invention employ an arm laterally extending from the body of the carabiner to define a major opening and a captive eye opening within the interior of the carabiner. Some of the inventive carabiner designs provide the capability of opening the gate while the captive eye opening is maintained. Methods of fabrication and use of the carabiners are also disclosed.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: June 12, 2007
    Assignee: Techxotic LC
    Inventor: Rocke P. Thompson
  • Patent number: D545973
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: July 3, 2007
    Assignee: Leto Holdings, LLC
    Inventors: Steven D. Powell, Kent W. Savage, David Meyers