Abstract: Systems and methods are provided for performing digital signing and encryption using identity-based techniques. A message may be signed and encrypted in a single operation and may be decrypted and verified in two separate operations. Messages may be sent anonymously and confidentially. The systems and methods support message confidentiality, signature non-repudiation, and ciphertext authentication, ciphertext unlinkability, and anonymity.

Abstract: A cavity antenna for an electronic device such as a portable computer is provided. The antenna may be formed from a conductive cavity and an antenna probe that serves as an antenna feed. The conductive cavity may have the shape of a folded rectangular cavity. A dielectric support structure may be used in forming the antenna cavity. A fin may protrude from one end of the dielectric support structure. The antenna probe may be formed from conductive structures mounted on the fin. An inverted-F antenna configuration or other antenna configuration may be used in forming the antenna probe. The electronic device may have a housing with conductive walls. When the cavity antenna mounted within an electronic device, a planar rectangular end face of the fin may protrude through a thin rectangular opening in the conductive walls to allow the antenna to operate without being blocked by the housing.

Abstract: An inverted-F antenna is provided that has a resonating element arm and a ground element. A shorting branch of the resonating element arm shorts the resonating element arm to the ground element. An antenna feed that receives a transmission line is coupled to the resonating element arm and the ground element. One or more impedance discontinuity structures are formed along the resonating element arm at locations that are between the shorting branch and the antenna feed. The impedance discontinuity structures may include shorting structures and capacitance discontinuity structures. The impedance discontinuity structures may be formed by off-axis vertical conductors such as vias that pass through a dielectric layer separating the antenna resonating element arm from the ground element. Capacitance discontinuity structures may be formed from hollowed portions of the dielectric or other dielectric portions with a dielectric constant that differs from that of the dielectric layer.

Abstract: A portable electronic device is provided that has a hybrid antenna. The hybrid antenna may include a slot antenna structure and a planar inverted-F antenna structure. The planar inverted-F antenna structure may be formed from traces on a flex circuit substrate. A backside trace may form a series capacitance for the planar inverted-F antenna structure. The antenna slot may have a perimeter that is defined by the location of conductive structures such as flex circuits, metal housing structures, a conductive bezel, printed circuit board ground conductors, and electrical components. Springs may be used in electrically connecting these conductive elements. A spring-loaded pin may be used as part of an antenna feed conductor. The pin may connect a transmission line path on a printed circuit board to the planar inverted-F antenna structure while allowing the planar inverted-F antenna structure to be removed from the device for rework or repair.

Abstract: Integrated circuits with guard rings are provided. Integrated circuits may include internal circuitry that is sensitive to external noise sources. A guard ring may surround the functional circuitry to isolate the circuitry from the noise sources. The guard ring may include first, second, and third regions. The first and third regions may include p-wells. The second region may include an n-well. Stripes of diffusion regions may be formed at the surface of a substrate in the three regions. Areas in the guard ring that are not occupied by the diffusion regions are occupied by shallow trench isolation (STI) structures. Stripes of dummy structures may be formed over respective STI structures and may not overlap the diffusion regions. The diffusion regions in the first and third regions may be biased to a ground voltage. The diffusion regions in the second section may be biased to a positive power supply voltage.

Abstract: Handheld electronic devices are provided that contain wireless communications circuitry having at least first and second antennas. An antenna isolation element reduces signal interference between the antennas, so that the antennas may be used in close proximity to each other. A planar ground element may be used as a ground by the first and second antennas. The first antenna may be formed using a hybrid planar-inverted-F and slot arrangement in which a planar resonating element is located above a rectangular slot in the planar ground element. The second antenna may be formed from an L-shaped strip. The planar resonating element of the first antenna may have first and second arms. The first arm may resonate at a common frequency with the second antenna and may serve as the isolation element. The second arm may resonate at approximately the same frequency as the slot portion of the hybrid antenna.

Abstract: A verifiable duplex multiplier circuit is provided. In one mode, the circuitry of the duplex multiplier functions as an N-bit×N-bit multiplier. In another mode, the circuitry of the duplex multiplier operates as dual N/2-bit×N/2-bit multipliers. Because the same circuitry can be used to serve as both an N×N multiplier and as dual N/2×N/2 multipliers, integrated circuit resources are conserved. The duplex multiplier circuitry uses an architecture that can be automatically synthesized using a logic synthesis tool. Verification operations can be performed using logic-equivalency error checking tools. Exhaustive verification is possible using this approach, even when relatively large duplex multipliers (e.g., duplex multipliers with N values of 16 or more) are used.

Abstract: Power regulator circuitry for programmable memory elements on programmable logic device integrated circuits is provided. The programmable memory elements may each include a storage element formed from cross-coupled inverters and an address transistor. Address drivers may be used to supply address signals to the address transistors. The power regulator circuitry may include an address power supply circuit that produces a time-varying address power supply voltage to the address drivers and storage element power supply circuits that provide time-varying storage element power supply voltages to the cross-coupled inverters in the storage elements. Unity gain buffers may be used to distribute a reference voltage from a bandgap voltage reference to the power supply circuits. The power supply circuits may use voltage dividers and p-channel metal-oxide-semiconductor control transistors.

Abstract: A system is provided that uses identity-based encryption to support secure communications between senders and recipients over a communications network. Private key generators are used to provide public parameter information. Senders encrypt messages for recipients using public keys based on recipient identities and using the public parameter information as inputs to an identity-based encryption algorithm. Recipients use private keys to decrypt the messages. There may be multiple private key generators in the system and a given recipient may have multiple private keys. Senders can include private key identifying information in the messages they send to recipients. The private key identifying information may be used by the recipients to determine which of their private keys to use in decrypting a message. Recipients may obtain the correct private key to use to decrypt a message from a local database of private keys or from an appropriate private key server.

Abstract: Programmable logic device integrated circuits with differential communications circuitry are provided in which the differential communications circuitry is used to support programming, testing, and user mode operations. Programming operations may be performed on a programmable logic device integrated circuit by receiving configuration data with the differential communications circuitry and storing the received configuration data in nonvolatile memory. The nonvolatile memory may be located in an external integrated circuit such as a configuration device or may be part of the programmable logic device integrated circuit. The stored configuration data may be loaded into configuration memory in the programmable logic device to program the device to perform a desired custom logic function. The differential communications circuitry may be used to handle boundary scan tests and programmable scan chain tests. During user mode operations the differential communications circuitry carries user data traffic.

Abstract: An integrated circuit with memory elements is provided. The memory elements may have memory element transistors with body terminals. Body bias control circuitry may supply body bias voltages that strengthen or weaken memory element transistors to improve read and write margins. The body bias control circuitry may dynamically control body bias voltages so that time-varying body bias voltages are supplied to memory element transistors. Address transistors and latch transistors in the memory elements may be selectively strengthened and weakened. Process variations may be compensated by weakening fast transistors and strengthening slow transistors with body bias adjustments.

Abstract: Arrays of memory elements may have data lines and address lines. Each memory element may have five transistors. An address decoder may receive an undecoded address signal and may produce a corresponding decoded address signal. The decoded version of the address signal may be used in addressing the memory elements in the memory array. The memory array may be loaded with configuration data. Loaded memory elements may each provide a static output control signal that configures a programmable logic transistor in programmable logic. The memory elements may be powered with an elevated voltage during normal operation. Boosted address signals may be used when addressing the memory array. The address decoder may contain circuitry that is responsive to a clear control signal and an address output enable signal. The memory element array may be cleared by asserting the clear control signal and address output enable signal.

Abstract: Slot antennas are provided for electronic devices such as portable electronic devices. The slot antennas may have a dielectric-filled slot that is formed in a ground plane element. The ground plane element may be formed from part of a conductive device housing. The slot may have one or more holes at its ends. The holes may affect the impedance characteristics of the slot antennas so that the length of the slot antennas may be reduced. For example, the holes can be used to synthesize the impedance of the slot antennas so that the slot antennas have a resonant frequency that is different from their natural resonant frequency. The holes may affect the impedance of the slot antennas in multiple radio-frequency bands.

Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.

Abstract: A URL verification service is provided that is used to evaluate the trustworthiness of universal resource locators (URLs). As a user browses the world wide web, the URL for a web page to which the user is browsing is evaluated. A brand and a second level domain portion may be extracted from the URL and used as search engine inputs in evaluating the trustworthiness of the URL. The content of the web page can also be analyzed. Page elements may be extracted from the web page and compared to page elements in a brand indicator table to identify page brands associated with the web page. The brand extracted from the URL is compared to the page brands to detect cross-branding. If cross-branding is detected, the URL verification service helps to prevent the user from submitting sensitive information over the internet.

Abstract: A serial communications protocol is provided that has mandatory features such as an idle code feature and optional features such as an optional automatic lane polarity reversal feature and an optional automatic lane order reversal feature, an optional clock tolerance compensation feature, an optional flow control feature, and an optional retry-on-error feature. A user that desires to create a protocol-compliant integrated circuit design can either choose to include or to not include the optional features. Integrated circuits in which the optional features are implemented are able to perform the associated functions. Integrated circuits in which the optional features have not been implemented are not able to perform these functions, but can be fabricated using fewer circuit resources.

Abstract: Integrated circuits are provided with circuitry such as multiplexers that can be selectively configured to route different adjustable power supply voltages to different circuit blocks on the integrated circuits. The circuit blocks may contain memory elements that are powered by the power supply voltages and that provide corresponding static output control signals at magnitudes that are determined by the power supply voltages. The control signals from the memory elements may be applied to the gates of transistors in the circuit blocks. Logic on an integrated circuit may be powered at a given power supply voltage level. The memory elements may provide their output signals at overdrive voltage levels that are elevated with respect to the given power supply voltage level. Memory elements associated with circuit blocks that contain critical paths can be overdriven at voltages that are larger than memory elements associated with circuit blocks that contain noncritical paths.

Abstract: Cryptographic systems and methods are provided in which authentication operations, digital signature operations, and encryption operations may be performed. Authentication operations may be performed using authentication information. The authentication information may be constructed using a symmetric authentication key or a public/private pair of authentication keys. Users may digitally sign data using private signing keys. Corresponding public signing keys may be used to verify user signatures. Identity-based-encryption (IBE) arrangements may be used for encrypting messages using the identity of a recipient. IBE-encrypted messages may be decrypted using appropriate IBE private keys. A smart card, universal serial bus key, or other security device having a tamper-proof enclosure may use the authentication information to obtain secret key information. Information such as IBE private key information, private signature key information, and authentication information may be stored in the tamper-proof enclosure.

Abstract: An integrated circuit inductor may have upper and lower loop-shaped line portions that are connected in series. The upper and lower portions may have 45° bends that form hexagonal or octagonal loops. Each loop portion may have one or more turns. Intervening metal-free regions of metal routing layers may be formed between the two layers to reduce capacitive coupling. Each loop portion may have sets of two or more metal lines shorted in parallel by vias. The upper and lower loops may be laterally offset or nested to reduce capacitive coupling.

Abstract: Transmission lines for electronic devices such as microstrip and stripline transmission lines may be provided that include patterned conductive lines and a conductive paint in the patterned conductive lines. The transmission lines may include one or more planar ground conductors. The ground conductors may include conductive lines arranged in a crosshatch pattern with spaces between the conductive lines. The ground conductors may also include conductive paint in spaces within the crosshatched pattern. The ground conductors may form one or more ground planes for the transmission lines.