Abstract: Integrated circuits with memory elements are provided. The memory elements may be arranged in an array. Data lines may be used to load data into the memory elements and may be used to read data from the memory elements. The memory elements may be used to store configuration data on a programmable logic device integrated circuit. Each memory element may have an output that supplies a programmable transistor gate with a static control signal. Data reading circuitry may be coupled to each data line to read data from an addressed memory element on that data line. The data reading circuitry for each data line may include a precharge transistor and an output latch. The output latch may contain cross-coupled inverters. An inwardly-directed inverter in the output latch may have a pull-up transistor that is connected in series with a current source.

Abstract: Power regulator circuitry for programmable memory elements on programmable logic device integrated circuits is provided. The programmable memory elements may each include a storage element formed from cross-coupled inverters and an address transistor. Address drivers may be used to supply address signals to the address transistors. The power regulator circuitry may include an address power supply circuit that produces a time-varying address power supply voltage to the address drivers and storage element power supply circuits that provide time-varying storage element power supply voltages to the cross-coupled inverters in the storage elements. Unity gain buffers may be used to distribute a reference voltage from a bandgap voltage reference to the power supply circuits. The power supply circuits may use voltage dividers and p-channel metal-oxide-semiconductor control transistors.

Abstract: Ring oscillator circuitry is provided. The ring oscillator circuitry may include a loop of inverters. A control gate may be interposed in the loop to control operation of the loop. The control gate may be activated using a ring oscillator trigger signal. During application of the trigger signal, the trigger signal may become degraded due to circuit parasitics. Trigger signal conditioning circuitry may be used to remove noise from the degraded trigger signal. A version of the trigger signal that has been conditioned by the trigger signal conditioning circuitry may be applied to a control input of the control gate. The trigger signal conditioning circuitry may include a low pass filter, a hysteresis circuit, and a two-stage buffer. The two-stage buffer may be formed from transistors with the same characteristics as the transistors in the inverters of the ring oscillator loop.

Abstract: A handheld electronic device may be provided that contains wireless communications circuitry. The handheld electronic device may have a housing and a display. The display may be attached to the housing a conductive bezel. The handheld electronic device may have one or more antennas for supporting wireless communications. A ground plane in the handheld electronic device may serve as ground for one or more of the antennas. The ground plane and bezel may define a opening. A rectangular slot antenna or other suitable slot antenna may be formed from or within the opening. One or more antenna resonating elements may be formed above the slot. An electrical switch that bridges the slot may be used to modify the perimeter of the slot so as to tune the communications bands of the handheld electronic device.

Abstract: Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of an array. The cyclic redundancy check error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry uses parallel processing to continuously monitor the data to identify the row and column location of each error.

Abstract: Computer aided design tools are provided that assist circuit designers in optimizing circuit performance. A circuit designer who is designing an integrated circuit may supply circuit design data and constraint data. Computer aided design tools may process the data to produce output data. The output data may include information on an implementation of the circuit design in a given type of integrated circuit device and may include report data on how the implementation of the circuit design is expected to perform. An optimization assistance tool analyzes the design and constraint data and the report data to identify potential problem areas. Recommendations may be provided to the circuit designer on how to address potential problems. Selectable options are displayed for the circuit designer. By selecting an appropriate option, the circuit designer can automatically launch a tool to make recommended settings adjustments.

Abstract: A portable computer is provided that has a housing. A battery may be contained within the housing. The housing may have panels such as a fixed housing panel and a removable access panel. A lever actuated latching mechanism may be used to lock the removable access panel and the battery within the portable computer. A lock may be used to block movement of the lever and thereby prevent access to the interior of the computer. Magnetic elements may be used to facilitate operation of the lever and to hold the access panel in place. The latch mechanism may provide mechanical advantage when disengaging the magnets that hold the access panel.

Abstract: A system is provided that uses identity-based encryption to support secure communications. Messages from a sender to a receiver may be encrypted using the receiver's identity and public parameters that have been generated by a private key generator associated with the receiver. The private key generator associated with the receiver generates a private key for the receiver. The encrypted message may be decrypted by the receiver using the receiver's private key. The system may have multiple private key generators, each with a separate set of public parameters. Directory services may be used to provide a sender that is associated with one private key generator with appropriate public parameters to use when encrypting messages for a receiver that is associated with a different private key generator. A certification authority may be used to sign directory entries for the directory service. A clearinghouse may be used to avoid duplicative directory entries.

Abstract: Handheld electronic devices are provided that contain wireless communications circuitry. The wireless communications circuitry may have first and second transceiver circuits that operate in the same radio-frequency band using different communications protocols. The wireless communications circuitry may have a configurable radio-frequency combiner and divider circuit that is coupled between an antenna and the first and second transceiver circuits. The combiner and divider circuit can be configured to support simultaneous use of the antenna by the first and second transceiver circuits. When simultaneous use is not required, the combiner and divider circuit can be used by either the first transceiver circuit or the second transceiver circuit.

Abstract: An integrated circuit is provided with groups of transistors that handle different maximum voltage levels. The transistors may be metal-oxide-semiconductor transistors having body, source, drain, and gate terminals. The gate of each transistor may have a gate insulator and a gate conductor. The gate conductor may be formed from a semiconductor such as polysilicon. Adjacent to the gate insulator, the polysilicon gate conductor may have a depletion layer. The depletion layer may have a thickness that is related to the doping level in the polysilicon gate conductor. By reducing the doping level in the polysilicon gates of some of the transistors, the equivalent oxide thickness of those transistors is increased, thereby enhancing their ability to withstand elevated voltages without experiencing gate oxide breakdown due to hot carrier injection effects.

Abstract: Handheld electronic devices are provided that contain wireless communications circuitry having at least first and second antennas. An antenna isolation element reduces signal interference between the antennas, so that the antennas may be used in close proximity to each other. A planar ground element may be used as a ground by the first and second antennas. The first antenna may be formed using a hybrid planar-inverted-F and slot arrangement in which a planar resonating element is located above a rectangular slot in the planar ground element. The second antenna may be formed from an L-shaped strip. The planar resonating element of the first antenna may have first and second arms. The first arm may resonate at a common frequency with the second antenna and may serve as the isolation element. The second arm may resonate at approximately the same frequency as the slot portion of the hybrid antenna.

Abstract: A compact magnetic cable noise suppressor may be provided for suppressing electromagnetic cable noise. The compact magnetic noise suppressor may be formed from a ferrite material or other magnetic material with a high permeability. The compact magnetic cable noise suppressor may be mounted within a chassis of a cable connector or may otherwise be attached to a cable. The magnetic cable noise suppressor may have portions that define a cable entrance, a cable exit, and a cable path. The cable path contains at least one bend. The cable path may contain multiple bends, may contain loops, may contain spirals, and may contain one or more vertically separated layers. The cable entrance and exit may be aligned or may be at different lateral or vertical positions. The cable entrance and exit may be on opposing sides of the noise suppressor or may be on adjacent sides of the noise suppressor.

Abstract: Antenna window structures and antennas are provided for electronic devices. The electronic devices may be laptop computers or other devices that have conductive housings. Antenna windows can be formed from dielectric members. The dielectric members can have elastomeric properties. An antenna may be mounted inside a conductive housing beneath a dielectric member. The antenna can be formed from a parallel plate waveguide structure. The parallel plate waveguide structure may have a ground plate and a radiator plate and may have dielectric material between the ground and radiator plates. The ground plate can have a primary ground plate portion and a ground strip. The ground strip may reflect radio-frequency signals so that they travel through the dielectric member. The antenna may handle radio-frequency antenna signals in one or more communications bands. The radio-frequency antenna signals pass through the dielectric member.

Abstract: Integrated circuits such as programmable logic device integrated circuits are provided with transmitter and receiver circuitry for communicating over multi-lane serial communications links. Data is transmitted over the serial communications links in the form of data packets. Priority data packets may be nested within regular data packets. Regular data packets may be formed using start-of-packet and end-of-packet markers. The locations at which priority packets are nested within regular data packets may be denoted using suspend and continuation markers. A single cyclic redundancy check generator may be used to generate cyclic redundancy check words for the data packets. Start-of-packet markers, end-of-packet markers, suspend markers, continuation markers, and cyclic redundancy check words may be inserted and extracted from the serial communications link at fixed lane locations.

Abstract: A programmable logic device integrated circuit or other integrated circuit may have logic circuitry that produces data signals. The data signals may be routed to other logic circuits through interconnects. The interconnects may be programmable. A level recovery circuit may be used at the end of each interconnect line to strengthen the transmitted data signal. The level recovery circuit that is attached to a given interconnect line may produce true and complementary versions of the data signal that is on that interconnect line. Level shifting circuitry may be provided to boost the data signals on the interconnects. Each interconnect line may have a level shifter circuit that receives the true and complementary versions of a data signal and that produces corresponding boosted true and complementary versions of the data signal. The boosted signals may be provided to the control inputs of complementary-metal-oxide-semiconductor transistor pass gates in programmable look-up table circuitry.

Abstract: A bid evaluation tool is provided for evaluating proposed bids for commodity sales contracts. The tool displays historical price data and forecasts in a graph. A user of the tool defines a date range for a proposed contract by entering starting and ending dates for the contract. The tool analyzes price data for the date range and generates a corresponding proposed bid for the date range. A bid window may be used to gather user inputs for the tool. The user can select between multiple bid pricing models for the bid evaluation tool to use when processing the price data to produce the proposed bid. Bid models for the tool include models such as a flat average model, a linear fit model, and an offset model. The user can adjust which historical data is included in the graph and can select which data set is used to generate bids.

Abstract: A programmable logic device that receives and stores configuration data in configurable random-access-memory has differential signal input buffer circuitry for receiving the configuration data from a configuration device in differential signal form at high speeds. The programmable logic device may have clock and data recovery circuitry that receives a reference clock and that generates a corresponding internal clock that is used for receiving the configuration data. Error detection circuitry may be used to detect errors occurring during data transmission. The configuration device may have a serializer that serializes parallel configuration data received from memory and differential signal output driver circuitry that provides the configuration data in differential signal form to the programmable logic device.

Abstract: A handheld bird identification tool is provided that assists users in identifying birds based on field observations. A user desiring assistance in classifying a bird uses interactive on-screen options to create a set of bird identification filter attributes. An interactive graphical view of a bird may be used to assign appearance characteristics such as color, pattern, and shape attributes to selected anatomical regions. The appearance characteristics and other filter attributes may be used as query terms in searching a bird identification database. A user may review audio clips of bird songs and images of birds matching the filter attributes. The bird identification tool may be used to manage a user's life list. Images, audio clips, and field notes may be gathered using the bird identification tool.

Abstract: Electronic devices may be provided with sensors for determining the presence and position of extendable and removable antennas. The antennas may extend by rotating about an axis, by reciprocating along their length, or by flexing from a retracted position to an extended position. The electronic device may determine when a removable antenna is attached or detached using signals from the sensors. The electronic device may determine the extent to which an antenna has been extended using signals from the sensors. The electronic device may control the operation of a radio-frequency transceiver that is coupled to the antenna based on signals from the sensors. The electronic device may turn the transceiver off when the antenna is retracted or removed. When the antenna is partially extended, the electronic device may place the transceiver in a low-power mode or place a dual-band transceiver into a single-band mode.

Abstract: Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) transistor serves as an electrically-programmable antifuse. The antifuse transistor has source, drain, gate, and substrate terminals. The gate has an associated gate oxide. In its unprogrammed state, the gate oxide is intact and the antifuse has a relatively high resistance. During programming, the gate oxide breaks down, so in its programmed state the antifuse transistor has a relatively low resistance. The antifuse transistor can be programmed by injecting hot carriers into the substrate of the device in the vicinity of the drain. Because there are more hot carriers at the drain than at the substrate, the gate oxide is stressed asymmetrically, which enhances programming efficiency. Feedback can be used to assist in turning the antifuse transistor on to inject the hot carriers.