Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract: A wafer of integrated circuits may be bonded to a carrier wafer using a layer of bonding material. The thickness of the wafer of integrated circuits may then be reduced using a series of grinding operations. After grinding, backside processing operations may be performed to form scribe channels that separate the die from each other and to form through-wafer vias. The scribe channels may be formed by dry etching and may have rectangular shapes, circular shapes, or other shapes. A pick and place tool may have a heated head. The bonding layer material may be based on a thermoplastic or other material that can be released by application of heat by the heated head of the pick and place tool. The pick and place tool may individually debond each of the integrated circuits from the carrier wafer and may mount the debonded circuits in packages.

Abstract: An integrated circuit has pins to which electrostatic discharge voltages may be delivered during electrostatic discharge events. Circuitry in the integrated circuit can be protected from damage by the electrostatic discharge voltages by electrostatic discharge protection circuitry. The electrostatic discharge protection circuitry may include one or more diodes that are connected between a given pin and ground to discharge negative electrostatic discharge voltages. Positive electrostatic discharge voltages may be discharged using a transistor that is connected between the pin and ground and that breaks down at a breakdown voltage. A voltage blocking circuit such as a circuit based on a voltage blocking transistor may be used to prevent damaging electrostatic discharge voltages from reaching sensitive circuitry. Pull down circuitry may be used to help ensure that the circuitry is protected from damage during electrostatic discharge events.

Abstract: An electronic device such as a computer monitor is provided that has an antenna that supports near field communications. The electronic device may have a housing with conductive housing surfaces. A display may be mounted in the housing. The conductive housing surfaces may contain a dielectric-filled hole. The antenna may have a substrate and one or more loops of conductive traces. The loops may exhibit mirror symmetry. The loops may overlap the display and the conductive housing surface. The loops may surround an inner loop-free portion of the antenna. The loop-free portion of the antenna may overlap the hole. Ferrite layers may be interposed between the loops of the antenna that overlap the display and the loops of the antenna that overlap the conductive housing.

Abstract: A portable computer is provided that has a housing. A removable battery may provide power to the portable computer. A connector on the battery may mate with a corresponding battery connector in the portable computer housing. The battery connector may be mounted in the portable computer housing using a floating arrangement. This allows the position of the connector to move slightly to accommodate variations in the position of the battery. A cable may be used to route power between the battery and a main logic board. A cover may be used to hold the battery connector and cable to the housing of the portable computer without excessively impeding movement of the connector.

Abstract: A system is provided that uses identity-based encryption (IBE) to allow a sender to securely convey information in a message to a recipient over a communications network. IBE public key information may be used to encrypt messages and corresponding IBE private key information may be used to decrypt messages. Information on which IBE public key information was used in encrypting a given message may be provided to the message recipient with the message. Multiple IBE public keys may be used to encrypt a single message. A less sensitive IBE public key may be used to encrypt a more sensitive public key, so that the more sensitive public key can remain hidden as it is sent to the recipient.

Abstract: Compact portable wireless devices and antennas for compact portable wireless devices are provided. The compact portable wireless device may be part of a piece of sports equipment. A compact portable wireless device may include a transceiver module that is used in communicating with equipment such as a handheld electronic device. An antenna for a compact portable wireless device can have a relatively small size while exhibiting high efficiency. A planar ground structure for the antenna may be formed from a circuit board on which integrated circuits have been mounted. A curved inverted-F resonating element may be attached to the ground structure. A battery may be provided to power the compact portable wireless device. The battery may be used as a parasitic antenna element.

Abstract: Programmable logic device integrated circuits with differential communications circuitry are provided in which the differential communications circuitry is used to support programming, testing, and user mode operations. Programming operations may be performed on a programmable logic device integrated circuit by receiving configuration data with the differential communications circuitry and storing the received configuration data in nonvolatile memory. The nonvolatile memory may be located in an external integrated circuit such as a configuration device or may be part of the programmable logic device integrated circuit. The stored configuration data may be loaded into configuration memory in the programmable logic device to program the device to perform a desired custom logic function. The differential communications circuitry may be used to handle boundary scan tests and programmable scan chain tests. During user mode operations the differential communications circuitry carries user data traffic.

Abstract: Dual port memory elements and memory array circuitry that utilizes elevated and non-elevated power supply voltages for performing reliable reading and writing operations are provided. The memory array circuitry may contain circuitry to switch a power supply line of a column of memory elements in the array to an appropriate power supply voltage during reading and writing operations. Each memory element may contain circuitry to select between power supply voltages during reading and writing operations. During reading operations, an elevated voltage may power cross-coupled inverters that store data in the memory elements while a non-elevated voltage may be used to turn on associated address transistors. During writing operations, the non-elevated voltage may power the cross-coupled inverters while the elevated voltage may be used to turn on the associated address transistors.

Abstract: Computer-aided-design tools are provided that support real-time phase-locked loop reconfiguration with a single design compilation. Each design compilation may involve operations such as logic synthesis and place and route operations. A circuit designer who is designing an integrated circuit may supply circuit design data. The circuit design data may include design data for multiple configurations of a phase-locked loop. By using a phase-locked loop scan chain initialization file generator engine located in a CAD tool design input wizard, the computer-aided-design tools may produce multiple phase-locked loop initialization files without performing a design compilation. The CAD tools may process one or more initialization files and the circuit design data to produce output data. The output data may include configuration data to implement the circuit design.

Abstract: Scan chain circuitry is provided for performing scan chain testing of integrated circuits. The integrated circuits being tested may include programmable logic. The scan chain circuitry may include scan chain cells. Each scan chain cell may have a first logic circuit that receives a scan enable signal. When the scan enable signal is asserted, the scan chain cells may be connected to form a scan chain for test data loading and unloading. Each scan chain cell may also include a second logic circuit. The second logic circuit in each scan chain cell may receive a test enable signal. Signal transitions may be created at the output of scan chain cells by loading the scan chain cells with data, deasserting the scan enable signal while the test enable signal is asserted, and applying a clock. At speed delay fault tests may be performed using the scan chain circuitry.

Abstract: Portable electronic devices are provided. Each device may be formed from two parts. A first part may be provided with components such as a display, a touch screen, a cover glass, and a frame. A second part may be provided with a plastic housing, circuit boards containing electrical components, and a bezel. Engagement members may be connected to the first and second parts. The engagement members may be formed from metal clips with holes and springs with flexible spring prongs that mate with the holes in the clips. The metal clips may be welded to frame struts on the frame and the springs may be welded to the bezel. During assembly, the first part may be rotated into place within the second part. Retention clips attached to the frame may be used to secure the two parts together. Assembly instructions and associated connector numbers may be provided within the devices.

Abstract: Handheld electronic devices are provided that contain wireless communications circuitry. The wireless communications circuitry has simultaneous reception functions that allow the handheld devices to simultaneously receive multiple communications signals in a single communications band. The handheld electronic devices may include cellular telephones with music player functionality or other portable devices. The handheld electronic devices may have local wireless communications capabilities for supporting local wireless links such as WiFi and Bluetooth links. Using the simultaneous reception functions of the wireless communications circuitry, users of the handheld electronic devices can simultaneously receive signals such as WiFi and Bluetooth signals.

Abstract: An image sensor may be formed from a planar semiconductor substrate. The image sensor may have an array of pixels. Each pixel may have a photosensitive element that is formed in the substrate and may have a light guide in a dielectric stack that guides light from a microlens and color filter to the photosensitive element. The light guides in pixels that are offset from the center of the image sensor may be tilted so that their longitudinal axes each form a non-zero angle with a vertical axis that lies perpendicular to the planar semiconductor substrate. These light guides may have laterally elongated openings that help collect light. A light guide may have a lower opening that matches the size of an associated photosensitive element. Photosensitive elements that are laterally offset from the center of the image sensor may be tilted. Pixels of different colors may have off-center photosensitive elements.

Abstract: A system is provided that uses cryptographic techniques to support secure messaging between senders and recipients. A sender may encrypt a message for a recipient using the recipient's public key. The sender may send the encrypted message to the message address of a given recipient. A server may be used to decrypt the encrypted message for the recipient, so that the recipient need not install a decryption engine on the recipient's equipment.

Abstract: A computer-based profit optimization model is provided that takes account of supply-side and demand-side factors in optimizing profit for an organization. The model takes into account which parts the organization uses to assemble various products. Demand curves are used to characterize the quantity of each product that will be demanded for various classes of product and classes of customer. Supply model data is used to determine which mix of products can be sold in view of parts availability. Using the demand model and supply model data, the optimization model can recommend a set of prices to use for selling the organization's products to various customers and at various shipment times. The model ensures that the organization has sufficient resources available to produce the products and enforces user-supplied business rules and other constraints.

Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. The memory elements may each have four inverter-like transistor pairs that form a bistable element and a pair of address transistors. There may be four nodes in the transistor each of which is associated with a respective one of the four inverter-like transistor pairs. There may be two control transistors each of which is coupled between the transistors in a respective one of the inverter-like transistor pairs. During data writing operations, the two control transistors may be turned off to temporarily decouple the transistors in two of the four inverter-like transistor pairs.

Abstract: Integrated circuits are provided that have memory arrays. The memory arrays may include rows and columns of data byte storage locations. To implement algorithms that that process data subwords, a memory array may be partitioned into individual memory banks each of which has its own associated data register and its own associated address decoder. Each address decoder may receive address signals from an associated multiplexer. Address mapping circuits may be used to distribute address signals to multiplexer inputs using an non-blocking memory architecture. The memory architecture allows collections of data bytes to be written and read from the memory array using column-wise and row-wise read and write operations. The data bytes that are written to the array and that are read from the array may be stored in adjacent data byte locations in the array.

Abstract: Portable electronic devices are provided with wireless circuitry that includes antennas and antenna isolation elements. The antennas may include antennas that have multiple arms and that are configured to handle communications in multiple frequency bands. The antennas may also include one or more antennas that are configured to handle communications in a single frequency band. The antennas may be coupled to different radio-frequency transceivers. For example, there may be first, second, and third antennas and first and second transceivers. The first and third antennas may be coupled to the first transceiver and the second antenna may be coupled to the second transceiver. The antenna isolation elements may be interposed between the antennas and may serve to reduce radio-frequency interference between the antennas. There may be a first antenna isolation element between the first and second antennas and a second antenna isolation element between the second and third antennas.

Abstract: Integrated circuits are provided that have memory elements. The memory elements may be organized in an array. Data such as programmable logic device configuration data may be loaded into the array using read and write control circuitry. Each memory element may store data using a pair of cross-coupled inverters. Power supply circuitry may be used to power the cross-coupled inverters. A positive power supply signal and a ground power supply signal may be provided to the inverters by the power supply circuitry. Each memory element may have an associated clear transistor. A clear control signal may be asserted to turn on the clear transistor when clearing the memory elements. A given one of the inverters in each memory element may be momentarily weakened with respect to the clear transistor in that memory element by using the power supply circuitry to temporarily elevate the ground power supply signal.