Patents Represented by Attorney Trop, Pruner & Hu, P.C.
  • Patent number: 8352779
    Abstract: In one embodiment, the present invention includes a method for receiving an indication of a loss of redundancy with respect to a pair of mirrored memory regions of a partially redundant memory system, determining new mirrored memory regions, and dynamically migrating information stored in the original mirrored memory regions to the new mirrored memory regions. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: January 8, 2013
    Assignee: Intel Corporation
    Inventors: Mallik Bulusu, Robert C. Swanson
  • Patent number: 8351384
    Abstract: A single format of MAC control message may be used for the addition, deletion, or rearrangement of users in a group within a wireless network. In some cases, a change in the nature of the group may be implemented immediately upon receipt of a positive acknowledgement. A mobile station may determine its ACID without maintaining information about the previous ACID or startup frame.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: January 8, 2013
    Assignee: Intel Corporation
    Inventors: Shweta Shrivastava, Rath Vannithamby, Yuval Lomnitz, Aran Bergman, Tom Harel
  • Patent number: 8352748
    Abstract: A processor-based system such as a wireless communication module may implement security functions in a cost effective fashion by providing a virtual memory space whose addresses may be recognized. The memory is integrated with an application processor. When those addresses are recognized, access to special security protocols may be allowed. In another embodiment, a variety of dedicated hardware cryptographic accelerators may be provided to implement security protocols in accordance with a variety of different standards. By optimizing the hardware for specific standards, greater performance may be achieved.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: January 8, 2013
    Assignee: Intel Corporation
    Inventor: John P. Brizek
  • Patent number: 8352656
    Abstract: In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: January 8, 2013
    Assignee: Intel Corporation
    Inventor: Ramakrishna Saripalli
  • Patent number: 8352764
    Abstract: In one embodiment, the present invention includes power control logic for squelch detection circuitry to enable selective enabling of one or more squelch detection circuits of an interconnect interface in a low power mode. The logic may include a squelch mode control register to select a first mode or a second mode of power control, a second register coupled to the squelch mode control register to receive software settings to indicate which squelch detect circuit(s) to disable in a low power state of the interconnect, and a detector to dynamically detect a logical lane zero of the interconnect in the second mode. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: January 8, 2013
    Assignee: Intel Corporation
    Inventors: Sin Tan, Sivakumar Radhakrishnan, Bruce A. Tennant, Jasper Balraj, Altug Koker
  • Patent number: 8352812
    Abstract: Embodiments of apparatuses and methods for protecting data storage structures from intermittent errors are disclosed. In one embodiment, an apparatus includes a plurality of data storage locations, execution logic, error detection logic, and control logic. The execution logic is to execute an instruction to generate a data value to store in one of the data storage locations. The error detection logic is to detect an error in the data value stored in the data storage location. The control logic is to respond to the detection of the error by causing the execution logic to re-execute the instruction to regenerate the data value to store in the data storage location, causing the error detection logic to check the data value read from the data storage location, and deactivating the data storage location if another error is detected.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: January 8, 2013
    Assignee: Intel Corporation
    Inventors: Xavier Vera, Jaume Abella, Javier Carretero Casado, Antonio González
  • Patent number: 8347035
    Abstract: A processor may comprise a core area, a control unit, an uncore area. The core area may comprise multiple processing cores and line-fill buffers. A first processing core of the core area may store a first weakly ordered transaction in a first line-fill buffer. The firs processing core may offload the first weakly ordered transaction to the extended buffer space provisioned in the uncore area after receiving a request from the uncore area. The first processing core may then de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space. The uncore may then post the first weakly ordered transaction to a memory or a memory system. The control unit may track the first weakly ordered transaction to ensure that the first weakly ordered transaction is posted to the memory or the system.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: January 1, 2013
    Assignee: Intel Corporation
    Inventors: Geeyarpuram N. Santhanakrishnan, Julius Mandelblat, Ehud Cohen, Larisa Novakovsky, Zeev Offen, Michelle J. Moravan, Shlomo Raikin, Ron Gabor
  • Patent number: 8346202
    Abstract: In one embodiment, the present invention is directed to an apparatus configured to perform channel filtering operations digitally, to reduce area and power consumption as compared to analog filtering. After passive filtering of downconverted analog baseband signals, the signals are provided to digitization circuitry to convert the filtered baseband signals into digital signals. Then a digital circuit, which may be implemented as a digital signal processor (DSP), may channel filter the digital signals and provide the filtered digital signals to conversion circuitry to convert the channel filtered digital signals back to analog signals.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: January 1, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: Abdulkerim L. Coban, Aslamali A. Rafi
  • Patent number: 8344808
    Abstract: Embodiments are directed to capacitance compensation via a compensation device coupled to a gain device to compensate for a capacitance change occurring due to an input signal change, along with a controller coupled to the compensation device to receive the input signal and to control an amount of compensation based on the input signal. In some embodiments, banks may be formed of multiple compensation devices, where each of the banks has a different size and is coupled to receive a different set of bias voltages.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: January 1, 2013
    Assignee: Javelin Semiconductor, Inc.
    Inventors: Anil Samavedam, David E. Bockelman, Vishnu Srinivasan, Eric Kimball
  • Patent number: 8347038
    Abstract: In one embodiment, the present invention includes a method to obtain topology information regarding a system including at least one multicore processor, provide the topology information to a plurality of parallel processes, generate a topological map based on the topology information, access the topological map to determine a topological relationship between a sender process and a receiver process, and select a given memory copy routine to pass a message from the sender process to the receiver process based at least in part on the topological relationship. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: January 1, 2013
    Assignee: Intel Corporation
    Inventors: Sergey I Sapronov, Alexey V. Bayduraev, Alexander V. Supalov, Vladimir D. Truschin, Igor Ermolaev, Dmitry Mishura
  • Patent number: 8347127
    Abstract: A technique to adjust a processor's operating voltage dynamically while preventing a user from placing the processor into a harmful operating voltage state in relation to the core/bus frequency ratio of the processor. More particularly, embodiments of the invention relate to a technique to control the operating voltage of the processor as a function of the processor's bus and/or core clock frequency.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: January 1, 2013
    Assignee: Intel Corporation
    Inventor: Paul Zagacki
  • Patent number: 8346198
    Abstract: In one embodiment, the present invention includes an amplifier having a transistor stage coupled between a supply voltage and a bias current. The transistor stage has an input to receive a radio frequency (RF) input signal obtained from an antenna. The amplifier has an input impedance that is unmatched to a source impedance of the antenna. In some embodiments, this unmatched input impedance may be substantially greater than the source impedance, and may further be controlled based on a strength of the RF input signal.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: January 1, 2013
    Assignee: Silicon Laboratories Inc.
    Inventors: Dan B. Kasha, G. Tyson Tuttle, Gregory A. Hodgson
  • Patent number: 8340280
    Abstract: In one embodiment, an encryption operation may be performed by obtaining a product of a carry-less multiplication using multiple single instruction multiple data (SIMD) multiplication instructions each to execute on part of first and second operands responsive to an immediate datum associated with the corresponding instruction, and reducing the product modulo g to form a message authentication code of a block cipher mode. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: December 25, 2012
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Michael Kounavis
  • Patent number: 8341356
    Abstract: Embodiments of the present invention provide a secure programming paradigm, and a protected cache that enable a processor to handle secret/private information while preventing, at the hardware level, malicious applications from accessing this information by circumventing the other protection mechanisms. A protected cache may be used as a building block to enhance the security of applications trying to create, manage and protect secure data. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: December 25, 2012
    Assignee: Intel Corporation
    Inventors: Shlomo Raikin, Shay Gueron, Gad Sheaffer
  • Patent number: 8341486
    Abstract: A method for controlling power consumption of an iterative decoder based on one or more criteria is described. The method may include performing iterative decoding on a demodulated signal to provide a decoded signal, determining whether the iterative decoding is suffering an impairment, and terminating the iterative decoding responsive to the determination of the impairment, otherwise continuing the iterative decoding to provide the decoded signal.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: December 25, 2012
    Assignee: Silicon Laboratories Inc.
    Inventors: David Rault, Olivier Souloumiac
  • Patent number: 8331459
    Abstract: In one embodiment of the invention, an apparatus may comprise a memory to receive original video data that includes a continuity of time stamps and a discontinuity of time stamps. A processor may shift a first time stamp from the continuity of time stamps to the discontinuity of time stamps by an adaptively modified distance and play the shifted time stamp in a smooth fashion.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: December 11, 2012
    Assignee: Intel Corporation
    Inventor: Nikolay Alekseenko
  • Patent number: 8332857
    Abstract: A database system includes an optimizer to generate resource estimates regarding execution of a request in the database system, and a regulator to monitor execution of a request and to adjust a priority level of the request based on the monitored execution and based on the resource estimates provided by the optimizer.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: December 11, 2012
    Assignee: Teradota US, Inc.
    Inventors: Douglas Brown, Stephen Brobst, Anita Richards, Todd Walter
  • Patent number: 8331021
    Abstract: An optical sight includes an outer barrel unit, an objective lens unit, an ocular lens unit, a magnification unit, and an illumination unit. The outer barrel unit extends about an axis and has a front end and a rear end. The objective lens unit is mounted to the front end of the outer barrel unit and has a first optical axis. The ocular lens unit is mounted to the rear end of the outer barrel unit. The magnification unit is disposed in and on the outer barrel unit between the objective lens unit and the ocular lens unit, and has a second optical axis. The illumination unit is disposed on the magnification unit, and includes a light source spaced apart from the second optical axis, and a reflective element for projecting emitted light, which is emitted from the light source, onto the objective lens unit.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: December 11, 2012
    Assignee: Asia Optical Co., Inc.
    Inventor: Chen-Yeh Lin
  • Patent number: 8332373
    Abstract: A database system constructs representation for predicate expressions invoking user-defined routines. A first representation is constructed if an indicator has a first value, and a second representation is constructed if the indicator has a second value. Based on which representation is used, an optimizer in the database system selects use of indexing and/or statistics and/or other performance-enhancement features in generating a query plan.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: December 11, 2012
    Assignee: Teradata US, Inc.
    Inventor: Gregory H. Milby
  • Patent number: 8327415
    Abstract: In one embodiment, the present invention includes a method for setting an extensible policy mechanism to protect a root data structure including a page table, interpreting a bytecode of a pre-boot driver in a byte code interpreter, and controlling access to a memory location based on the extensible policy mechanism. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: December 4, 2012
    Assignee: Intel Corporation
    Inventors: Jiewen Yao, Liang Cui, Qin Long, Vincent J. Zimmer