Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for receiving a first portion of a first packet at a first agent and determining whether the first portion is an interleaved portion based on a value of an interleave indicator. The interleave indicator may be sent as part of the first portion. In such manner, interleaved packets may be sent within transmission of another packet, such as a lengthy data packet, providing improved processing capabilities. Other embodiments are described and claimed.

Abstract: Super-resolution images may be produced by dividing a higher resolution image into a set of non-overlapping rectangular tiles of substantially the same size. Then, each pixel in each lower resolution image is mapped to the higher resolution image and it is determined which tiles are mapped to which lower resolution image pixels. A continuous buffer may be allocated for each tile and the relevant lower resolution pixels may be stored, together with optical flow vectors, in that continuous buffer. Then, the determination of gradients may use the information now stored in the buffer to facilitate symmetric multiprocessing using multi-core processors.

Abstract: In one embodiment, a receiver includes parallel paths for signal channel processing and image channel processing. The paths may include a mixer to receive an intermediate frequency (IF) signal and to downconvert the IF signal to a channel baseband signal, a filter to generate a filtered channel value, a combiner to combine the channel baseband signal with a filtered channel value from the other path to obtain a channel path output, in addition to one or more controllers to generate a step control signal and update a weighting of the filters based at least in part on the step control signal.

Abstract: Methods, systems and machine readable media are disclosed for performing dynamic information flow tracking. One method includes executing operations of a program with a main thread, and tracking the main thread's execution of the operations of the program with a tracking thread. The method further includes updating, with the tracking thread, a taint value associated with the value of the main thread to reflect whether the value is tainted, and determining, with the tracking thread based upon the taint value, whether use of the value by the main thread violates a specific security policy.

Abstract: A backrest device for a chair includes two lateral pipe units, each including a backrest mounting pipe member and a coupling pipe member, and a backrest unit. The backrest mounting pipe member has a main surrounding wall defining a surrounding space therein, and a convex groove-defining wall disposed in the surrounding space and defining an engaging groove therein. The coupling pipe member has a coupling surrounding wall coupled to a lower end of the main surrounding wall, and an abutting wall for closing a top end of the coupling surrounding wall. The backrest unit includes a backrest member having opposite lateral portions each forming a rod-receiving loop, and two positioning rods sleeved respectively in the rod-receiving loops. Each lateral portion and a respective positioning rod are retained within the engaging groove of a corresponding pipe unit.

Abstract: An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein.

Abstract: A security protocol may be implemented on a processor-based system by providing a wireless signal to a handheld device normally carried by the user. If a response is not received, it may be determined that the user is not sufficiently proximate to the device being accessed and that, therefore, the person accessing the device is not authorized. An appropriate security protocol may be implemented as a result.

Abstract: In one embodiment, the present invention includes a mixer circuit to receive and generate a mixed signal from a radio frequency (RF) signal and a master clock signal, a switch stage coupled to an output of the mixer circuit to rotatingly switch the mixed signal to multiple gain stages coupled to the switch stage, and a combiner to combine an output of the gain stages.

Abstract: Machine-readable media, methods, apparatus and system are described. In an embodiment, a model client platform may generate a file image comprising an incremental file stored on a first model block of a model storage unit of the model client platform; generate a file description image comprising file description stored on a second model block of the model storage unit, wherein the file description comprises a position of the first model block in the model storage unit; and upload the file image and the file description image to a server connecting with the model client platform. An ordinary client platform may generate an ordinary block bitmap indicating usage status for each ordinary block of an ordinary storage unit of the ordinary client platform; and receive the file description image from the server connecting with the ordinary client platform.

Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

Abstract: In one implementation, a receiver may have an analog front end with an amplifier to receive a radio frequency (RF) signal and a mixer to downconvert the signal to a baseband signal. Then, a demodulator may receive the baseband signal and obtain an audio signal therefrom. Still further, a controller may be coupled to receive a control signal corresponding to a variable impedance level, and control a local oscillator coupled to the mixer responsive to the control signal. The variable impedance may be controlled by a user to tune to the channel.

Abstract: In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for generating a hybrid error correction code for a data block. The hybrid code, which may be a residual arithmetic-Hamming code, includes a first residue code based on the data block and a first parity code based on the data block and a Hamming matrix. Then the generated code along with the data block can be communicated through at least a portion of a datapath of a processor. Other embodiments are described and claimed.

Abstract: Apparatuses, methods, and systems for reconfiguring a secure system are disclosed. In one embodiment, an apparatus includes a configuration storage location, a lock, and lock override logic. The configuration storage location is to store information to configure the apparatus. The lock is to prevent writes to the configuration storage location. The lock override logic is to allow instructions executed from sub-operating mode code to override the lock.

Abstract: In one embodiment, the present invention includes an apparatus having a register file to store vector data, an address generator coupled to the register file to generate addresses for a vector memory operation, and a controller to generate an output slice from one or more slices each including multiple addresses, where the output slice includes addresses each corresponding to a separately addressable portion of a memory. Other embodiments are described and claimed.

Abstract: In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first core, cache coherency state information associated with the cache line is not updated. A coherence engine associated with the processor may receive the data access request and determine that the data is of a memory page owned by the first core and convert the data access request to a non-cache coherent request. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes semiconductor integrated code (SIC) corresponding to platform independent code of a processor manufacturer. This code may include embedded memory code (EMC) to initialize a memory via initialization of a memory controller, and a mapping of memory signals using an on-die termination (ODT) data structure accessible via the EMC, where the ODT data structure is provided by an original equipment manufacturer (OEM) and corresponds to a parameterized rule set for a platform dependent memory configuration of the memory. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for initializing a common information model (CIM) broker and a SLP service agent of a system in a pre-boot environment, transmitting a multicast request and receiving a unicast advertisement from a directory agent, registering a web-based enterprise management (WBEM) service to the directory agent, and configuring, provisioning, and/or performing asset inventory of the system in the pre-boot environment responsive to information from a resource manager. Other embodiments are described and claimed.

Abstract: For a given pool of database requests, a database system generates an integrated execution plan for multiple ones of the database requests in the pool. The database system determines whether to execute the integrated execution plan or individual execution plans corresponding to the respective multiple database queries. The determining is based on one or more criteria including performance goals corresponding to the respective multiple database requests.