Abstract: A liquid crystal display (LCD) device including a backlight module and an LCD panel is provided. The backlight module is used for providing light penetrating through the LCD panel disposed at one side of the backlight module. The LCD panel includes a substrate, a scan line, a first and a second data line, a first and a second switch element and a first and a second pixel electrode. The scan line and the two data lines, which are perpendicular to the scan line, are disposed on the substrate. The switch elements are respectively disposed at the intersection of the scan line and the first data line and the intersection of the scan line and the second data line. The pixel electrodes are respectively electrically connected to the switch elements. The area of the first pixel electrode is substantially less than that of the second one.

Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

Abstract: A flicker filter is adjusted according to degree of alpha blending performed on a display signal. For some weakly showing graphics images, a lower flicker filter level may be implemented or the flicker filter may be turned off. A threshold for turning off the flicker filter may be programmable. Other embodiments are described and claimed.

Abstract: In some embodiments, the Navier-Stokes matrix A may be developed on the fly using arrays of Dirichlet and von Neumann boundary conditions. As a result, the storage requirements are dramatically reduced and hardware accelerators or single instruction multiple data processors may be used to solve the Navier-Stokes equations.

Abstract: In one embodiment, the present invention includes a method for determining if a frequency control instruction would cause a first capacitor bank to reach a limit and adjusting the first capacitor bank in a first direction using a calibration value and adjusting a second capacitor bank in a second direction if the first capacitor bank would reach the limit. Furthermore, the calibration value may be calculated and stored in accordance with other embodiments. In such manner, small changes in capacitance and correspondingly small changes in frequency may be effected.

Abstract: A heart valve holder-inserter (21, 121) is designed to facilitate easy implantation of a mechanical heart valve prosthesis (23, 123). This holder-inserter, at its distal end, incorporates a pair of diametrically opposed guide members (47, 49, 81, 147, 149) which extend well beyond the leading edge of the prosthesis and which have exterior surfaces (53, 83, 153) of substantial dimension that are smoothly curved and proportioned so as to slowly spread the tissue annulus in order to facilitate easy entrance thereinto of the leading edge portion of the mechanical valve body.

Abstract: A liquid crystal display and a control method thereof are disclosed. The pixel of the liquid crystal display comprises: a first switch element, a second switch element, a first storage capacitor, a second storage capacitor, a first liquid crystal capacitor, and a second liquid crystal capacitor. The control method comprises: providing a first sub-pixel charge stage, a second sub-pixel charge stage, and a normal display stage. The first sub-pixel charge stage comprises: turning on the first switch element and the second switch to input a first gray level signal to the first storage capacitor, the second storage capacitor, the first liquid crystal capacitor, and the second liquid crystal capacitor. The second sub-pixel charge stage comprises: turning off the second switch element and inputting a second gray level signal to the first storage capacitor and the first liquid crystal capacitor. The normal display stage comprises: turning off the first switch element.

Abstract: Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant processing overhead.

Abstract: A cache that supports sub-socket partitioning is discussed. Specifically, the cache supports different quality of service levels and victim cache line selection for a cache miss operation. The different quality of service levels allow for programmable ceiling usage and floor usage thresholds that allow for different techniques for victim cache line selection.

Abstract: A liquid crystal display is provided. The liquid crystal display includes a rear bezel, a signal controlling board module, a light source module, a clipping frame, a display panel and a front frame. The rear bezel has a main portion, a receptacle and a plurality of carrying stages. The carrying stages surround the receptacle. The receptacle protrudes from the main body along a direction while the carrying stages protrude from the main portion toward the reverse of the direction. The main body, the receptacle and the carrying stages are formed in one piece. The signal controlling board module is fixed in the receptacle. The carrying stages carry the light source module. The clipping frame and the rear bezel clip the light source module together. The display panel is disposed on the clipping frame. The front frame and the clipping frame clip the display panel together.

Abstract: In one embodiment, the present invention includes a method of determining a relative priority between a first agent and a second agent, and assigning the first agent to a first channel and the second agent to a second channel according to the relative priority. Depending on the currently programmed status of the channels, information stored in at least one of the channels may be dynamically migrated to another channel based on the assignments. Other embodiments are described and claimed.

Abstract: Disclosed are methods, machine readable medium and systems that dynamically translate binary programs. The dynamic binary translation may include identifying a hot code trace of a program. The translation may further include determining a completion ratio for the hot code trace. The translation may also include packaging the hot code trace into a transactional memory region in response to the completion ratio having a predetermined relationship to a threshold ratio.

Abstract: A computer implemented method of manipulating and displaying an MPEG stream is described. In one embodiment of the invention, a computer implemented method comprises defining a spatial location across a series of pictures of an MPEG stream; and for each picture of the series of pictures in the MPEG stream, partially decoding the picture to determine an area of the picture falling within the spatial location.

Abstract: One aspect of the present invention is directed to an apparatus to perform impulse blanking of a received signal at multiple locations of a signal processing path. To effect such impulse blanking, multiple impulse detectors and blankets may be present, in addition to other circuitry. The impulse detectors may operate at different bandwidths, and the impulse blankers may be located at different locations of the signal processing path and may be differently configured.

Abstract: In accordance with one embodiment of the present invention, a first pixel of an LCD panel is driven via a first scan line to a first pixel voltage during a first scan period and to a second pixel voltage during a second scan period. Also, a second pixel is driven via the first scan line and a second scan line to the first pixel voltage during the first scan period.

Abstract: An active management technology device may be provisioned using a live operating system stored on a disk, in one embodiment. After disk insertion, no further operator involvement may be needed in some cases.

Abstract: A device having multiple cores executes an algorithm to control Thin-Film Thermoelectric Coolers (TFTEC) that employ the Peltier effect to remove heat from the various cores of the multi-core processor. The algorithms may combine Thread Migration (TM) and Dynamic Voltage/Frequency Scaling (DVFS) to provide Dynamic Thermal Management (DTM) and TFTEC control.

Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

Abstract: In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed.

Abstract: An array is formed by a plurality of cells, wherein each cell is formed by a bipolar junction selection transistor having a first, a second, and a control region. The cell includes a common region, forming the second regions of the selection transistors, and a plurality of shared control regions overlying the common region. Each shared control region forms the control regions of a plurality of adjacent selection transistors and accommodates the first regions of the plurality of adjacent selection transistors as well as contact portions of the shared control region. Blocks of adjacent selection transistors of the plurality of selection transistors share a contact portion and the first regions of a block of adjacent selection transistors are arranged along the shared control region between two contact portions.