Patents Represented by Attorney Trop, Pruner & Hu, P.C.

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  • Transforming a data type of a column in a table
    Patent number: 8126900
    Abstract: A database system receives a transaction that selects values of a column of a first table based on one or more conditions, the column in the first table being according to a first data type. The database system transforms the first data type to a second, different data type. The selected values of the column according to the second data type are stored in the second table.
    Type: Grant
    Filed: February 3, 2004
    Date of Patent: February 28, 2012
    Assignee: Teradata US, Inc.
    Inventors: O. Pekka Kostamaa, J. Mark Morris
  • Enabling graphical notation for parallel programming
    Patent number: 8127283
    Abstract: In one embodiment, the present invention includes a method for developing of a parallel program by specifying graphical representations for input data objects into a parallel computation code segment, specifying graphical representations for parallel program schemes, each including at least one graphical representation of an operator to perform an operation on an data object, determining if any of the parallel program schemes include at least one alternative computation, and unrolling the corresponding parallel program schemes and generating alternative parallel program scheme fragments therefrom. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: February 28, 2012
    Assignee: Intel Corporation
    Inventors: Yuriy E. Sheynin, Alexey Y. Syschikov
  • High hole mobility semiconductor device
    Patent number: 8124959
    Abstract: One embodiment of the invention includes a high hole mobility p-channel GaAsySb1-y quantum well with a silicon substrate and an InxAl1-xAs barrier layer.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: February 28, 2012
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Suman Datta, Robert S. Chau, Marko Radosavljevic
  • Method and apparatus for booting a processing system
    Patent number: 8127363
    Abstract: Machine-readable media, methods, apparatus and system for booting a processing system are described. In an embodiment, whether to launch an open operating system or a closed operating system to boot a processing system may be determined. A key may be retrieved from a processor register of the processing system and used to decrypt an encrypted version of the closed operating system based at least in part on a determination of booting the processing system with the closed operating system. In another embodiment, the processor register stored with the key may be flushed based at least in part on a determination of booting the processing system with the open operating system.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: February 28, 2012
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Konstantin Levit-Gurevich, Boaz Ouriel, Israel Hirsh
  • Correcting for phase noise of an oscillator
    Patent number: 8126420
    Abstract: In one embodiment, the present invention includes a method for digitizing a phase noise value indicative of a level of phase noise present in a LO signal and downconverting an RF signal to a second frequency signal using the LO signal. This downconversion can cause the phase noise to be transferred to the second frequency signal. The method may thus further include removing the phase noise from the second frequency signal using the digitized phase noise value.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: February 28, 2012
    Assignee: Silicon Laboratories Inc.
    Inventors: Mustafa H. Koroglu, G. Tyson Tuttle, Peter J. Vancorenland, Alessandro Piovaccari
  • Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor
    Patent number: 8127085
    Abstract: Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: February 28, 2012
    Assignee: Intel Corporation
    Inventors: Lihu Rappoport, Chen Koren, Franck Sala, Oded Lempel, Ido Ouziel, Ilhyun Kim, Ron Gabor, Lior Libis, Gregory Pribush
  • Image acquiring device with positioning assisting functionality
    Patent number: 8120657
    Abstract: An image acquiring device with positioning assisting functionality is for acquiring an image of an object to be captured, and includes a positioning assisting unit and an image acquiring unit. The positioning assisting unit emits light toward a planar surface. The light forms at least one positioning mark on the planar surface. The image acquiring unit is for acquiring an image of an image acquiring region associated with the positioning mark.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: February 21, 2012
    Assignee: Wistron Corporation
    Inventors: Chia-Hsien Li, Wei Kuo Lee, Kuo Kun Lin
  • Method, apparatus, and system for dynamic ECC code rate adjustment
    Patent number: 8122323
    Abstract: A method, apparatus, and system for dynamic adjustment of an error control coding (ECC) code rate are disclosed. In one embodiment, a code rate may be changed from a first code rate to a second code rate in response to a change in a bit error rate.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: February 21, 2012
    Assignee: Intel Corporation
    Inventors: Peter Leung, Chun Fung Man, Chong Ong
  • Method and apparatus for controlling inertial system
    Patent number: 8120303
    Abstract: Suppression of vibration of a load machine without reducing the responsiveness of the load machine to an operation command is achieved by a method and an apparatus for controlling an inertial system intended to control an inertial system that has a motive power generator and a load machine that are coupled to each other via a torque transmission element. Acceleration command information that designates the acceleration of the load machine is multiplied by a predetermined gain to produce a vibration suppression control variable. The vibration suppression control variable is added to the position command to form a vibration suppression control command, and the inertial system is controlled according to the vibration suppression control command.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: February 21, 2012
    Assignee: Oriental Motor Co., Ltd.
    Inventors: Tsuyoshi Kumagai, Zhenghua Luo
  • Unidirectional sweep training for an interconnect
    Patent number: 8121239
    Abstract: In one embodiment, the present invention includes a receiver having a delay lock loop (DLL) to receive a clock signal and to generate a plurality of clock phases therefrom, and an offset controller including a first register set for a first phase interpolator and a second register set for a second phase interpolator. At initiation of a track pre-tune process, both phase interpolators are controlled to generate sampling signals at a common clock phase. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: February 21, 2012
    Assignee: Intel Corporation
    Inventors: Liang Yin, Harry Muljono, Sunil Kumar, Alex Kuperman
  • Transaction manager and cache for processing agent
    Patent number: 8122194
    Abstract: A processing agent is used in a system that transfers data of a predetermined data line length during external transactions. The agent may include an internal cache having a plurality of cache entries. Each cache entry may store multiple data line lengths of data. The agent further may include a transaction queue system having queue entries that include a primary entry including an address portion and status portion, the status portion provided for a first external transaction of the agent, and a secondary entry including a status portion provided for a second external transaction.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: February 21, 2012
    Assignee: Intel Corporation
    Inventors: Chinna Prudvi, Derek T. Bachand
  • Using a bit specific reference level to read a resistive memory
    Patent number: 8116159
    Abstract: A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: February 14, 2012
    Assignee: Ovonyx, Inc.
    Inventors: Tyler Lowrey, Ward D. Parkinson, Ferdinando Bedeschi, Claudio Resta, Roberto Gastaldi, Giulio Casagrande
  • Optimizing power usage by processor cores based on architectural events
    Patent number: 8117478
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: February 14, 2012
    Assignee: Intel Corporation
    Inventors: Yen-Cheng Liu, P Keong Or, Krishnakanth Sistia, Ganapati Srinivasa
  • Reducing common mode effects in an output stage
    Patent number: 8116700
    Abstract: In one embodiment, a power amplifier may include an output stage with multiple transformers and corresponding matching capacitances. The capacitances may include a first matching capacitance coupled in parallel with a secondary coil of a first transformer and a second matching capacitance coupled in parallel with a secondary coil of a second transformer, where the secondary coils are coupled in series in an output stack configuration. By accounting for parasitics present in the power amplifier, the first matching capacitance can be designed to have a greater capacitance than the second matching capacitor, even where the first and second transformers are configured to output substantially equal power levels.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: February 14, 2012
    Assignee: Javelin Semiconductor, Inc.
    Inventor: Eric Kimball
  • Optical sight for maintaining diopter adjustment
    Patent number: 8116007
    Abstract: An optical sight includes a main barrel unit, an objective lens unit, an ocular lens unit, and a magnification unit. The main barrel unit extends about an axis. The objective lens unit is mounted to a front end of the main barrel unit. The ocular lens unit is mounted to a rear end of the main barrel unit, and includes an outer barrel securely connected to the main barrel unit, an inner barrel coupled threadedly with the outer barrel, a lens disposed in the inner barrel, an adjusting barrel disposed on the inner barrel and movable in a direction along the axis, and a release device disposed between the inner barrel and the adjusting barrel. The magnification unit is rotatably disposed in the main barrel unit between the objective lens unit and the ocular lens unit.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: February 14, 2012
    Assignee: Asia Optical Co., Inc.
    Inventor: Chen-Shuo Tsai
  • Using affinity measures with supervised classifiers
    Patent number: 8117143
    Abstract: A non-binary affinity measure between any two data points for a supervised classifier may be determined. For example, affinity measures may be determined for tree, kernel-based, nearest neighbor-based and neural network supervised classifiers. By providing non-binary affinity measures using supervised classifiers, more information may be provided for clustering, analyzing and, particularly, for visualizing the results of data mining.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: February 14, 2012
    Assignee: Intel Corporation
    Inventor: Gary R. Bradski
  • Multiple compression techniques for packetized information
    Patent number: 8111704
    Abstract: In one embodiment, the present invention includes a method for comparing a packet header to a stored packet header, generating a comparison vector based on the comparison, and transmitting the packet from the transmitter without the packet header if the packet header and the stored packet header match. A data portion of the packet may be compressed and transmitted using a different compression technique. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: February 7, 2012
    Assignee: Intel Corporation
    Inventors: Abhishek Singhal, Debendra Das Sharma, Jesus Palomino, Mario A. Rubio
  • Loop detection in a communications network
    Patent number: 8107382
    Abstract: A first node includes ports and a controller to receive a test packet at a first one of the ports. The first node determines whether the received test packet has a destination address that matches one or more predefined addresses associated with a second node. Presence of a loop in a communications network in which the first and second nodes are located is indicated in response to detecting receipt of the test packet containing the matching destination address.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: January 31, 2012
    Assignee: Avaya Holdings Limited
    Inventors: Chuh Yu Lin, Roger Lapuh
  • Forward feature selection for support vector machines
    Patent number: 8108324
    Abstract: In one embodiment, the present invention includes a method for training a Support Vector Machine (SVM) on a subset of features (d?) of a feature set having (d) features of a plurality of training instances to obtain a weight per instance, approximating a quality for the d features of the feature set using the weight per instance, ranking the d features of the feature set based on the approximated quality, and selecting a subset (q) of the features of the feature set based on the ranked approximated quality. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: January 31, 2012
    Assignee: Intel Corporation
    Inventors: Eyal Krupka, Aharon Bar-Hillel
  • Chair
    Patent number: D654714
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: February 28, 2012
    Assignee: Taiwan Shin Yeh Enterprises Co., Ltd.
    Inventor: Chuen-Jong Tseng