Patents Represented by Attorney Trop, Pruner & Hu, P.C.

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  • Firmware security key upgrade algorithm
    Patent number: 8200988
    Abstract: A portion of a firmware program may be automatically upgraded during power on of a processor-based system. A firmware upgrade file signed by a private key is authenticated using a public key accessible to the firmware program. The authentication and upgrade is performed automatically. Interrupted upgrades are anticipated and resolved by the firmware program. The public key is duplicated and is itself upgradable, in case the private key changes. The firmware program may be locked to prevent both viewing and unauthorized upgrades of the public keys or other parts of the firmware program.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: June 12, 2012
    Assignee: Intel Corporation
    Inventors: Larry H. Gass, Chad W. Mercer, David A. Schollmeyer
  • Capacitive isolation circuitry
    Patent number: 8198951
    Abstract: An integrated circuit having voltage isolation capabilities includes a plurality of communications channels for transceiving data from the integrated circuit. Each of the communications channel includes capacitive isolation circuitry located in conductive layers of the integrated circuit for providing a high voltage isolation link. The capacitive isolation circuitry distributes a first portion of a high voltage isolation signal across a first group of capacitors on a first link and a second link in the capacitive isolation circuitry and distributes a second portion of the high voltage isolation signal across a second group of capacitors in the first link and the second link in the capacitive isolation circuitry. A differential receiver on each of the plurality of communications channels receives the data on the first link and the second link.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: June 12, 2012
    Assignee: Silicon Laboratories Inc.
    Inventors: Zhiwei Dong, Shouli Yan, Axel Thomsen, William W. K. Tang, Ka Y. Leung
  • Hybrid transactions for low-overhead speculative parallelization
    Patent number: 8195898
    Abstract: A method and apparatus for a hybrid transactional memory system is herein described. A first transaction is executed utilizing a first style of a transactional memory system and a second transaction is executed in parallel utilizing a second style of a transactional memory system. For example, a main thread is executed utilizing an update-in place Software Transactional Memory (STM) system while a parallel thread, such as a helper thread, is executed utilizing a write buffering STM. As a result, a main thread may directly update memory locations, while a helper thread's transactional writes are buffered to ensure they do not invalidate transactional reads of the main thread. Therefore, parallel execution of threads is achieved, while ensuring at least one thread, such as a main thread, does not degrade below an amount of execution cycles it would take to execute the main thread serially.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: June 5, 2012
    Assignee: Intel Corporation
    Inventors: Adam Welc, Ali-Reza Adl-Tabatabai
  • In-loop adaptive wiener filter for video coding and decoding
    Patent number: 8195001
    Abstract: A video encoder may use an adaptive Wiener filter inside the core video encoding loop to improve coding efficiency. In one embodiment, the Wiener filter may be on the input to a motion estimation unit and, in another embodiment, it may be on the output of a motion compensation unit. The taps for the Wiener filter may be determined based on characteristics of at least a region of pixel intensities within a picture. Thus, the filtering may be adaptive in that it varies based on the type of video being processed.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: June 5, 2012
    Assignee: Intel Corporation
    Inventors: Yi-Jen Chiu, Lidong Xu
  • Loop delay compensation for continuous time sigma delta analog to digital converter
    Patent number: 8195221
    Abstract: A continuous time sigma delta analog to digital converter may use a finite impulse response filter for delay compensation. In some embodiments, the filter may be simplified by using only the first and/or second filter coefficients.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: June 5, 2012
    Assignee: Intel Corporation
    Inventors: Simone Gambini, Hasnain Lakdawala
  • Forming a phase change memory with an ovonic threshold switch
    Patent number: 8188454
    Abstract: A phase change memory may include an ovonic threshold switch formed over an ovonic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: May 29, 2012
    Assignee: Ovonyx, Inc.
    Inventor: Charles H. Dennison
  • Optimizing concurrent accesses in a directory-based coherency protocol
    Patent number: 8190820
    Abstract: In one embodiment, the present invention includes a directory to aid in maintaining control of a cache coherency protocol. The directory can be coupled to multiple caching agents via an interconnect, and be configured to store a entries associated with cache lines. The directory also includes logic to determine a time delay before the directory can send a concurrent snoop request. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: May 29, 2012
    Assignee: Intel Corporation
    Inventors: Hariharan Thantry, Akhilesh Kumar, Seungjoon Park
  • Method and apparatus for performing cryptographic operations
    Patent number: 8189792
    Abstract: In one embodiment, the present invention includes a processor having logic to perform a round of a cryptographic algorithm responsive to first and second round micro-operations to perform the round on first and second pairs of columns, where the logic includes dual datapaths that are half the width of the cryptographic algorithm width (or smaller). Additional logic may be used to combine the results of the first and second round micro-operations to obtain a round result. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: May 29, 2012
    Assignee: Intel Corporation
    Inventors: Brent Boswell, Kirk Yap, Gilbert Wolrich, Wajdi Feghali, Vinodh Gopal, Srinivas Chennupaty, Makaram Raghunandan
  • Methods and apparatuses for controlling thread contention
    Patent number: 8190930
    Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: May 29, 2012
    Assignee: Intel Corporation
    Inventors: Andrew Herdrich, Ramesh Illikkal, Donald Newell, Ravishankar Iyer, Vineet Chadha
  • System for processor frequency governors to govern a processor frequency by deriving CPU utilization information based on the state of virtual machine monitor
    Patent number: 8191062
    Abstract: A method, apparatus and system enable processor frequency governors to comprehend virtualized platforms. Specifically, in one embodiment, the processor frequency governor in a virtual host may be para-virtualized. As a result, the processor frequency governor may run in a partition on the virtualized platform and nonetheless collect and process central processing utility (“CPU”) information on the virtualized platform based on the activity of a plurality of virtual machines on the virtual host.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: May 29, 2012
    Assignee: Intel Corporation
    Inventor: Steven Grobman
  • Data analysis based on manipulation of large matrices on a persistent storage medium
    Patent number: 8185547
    Abstract: Matrices involved in a data analysis are stored in predetermined blocks, where blocks for a first matrix contain respective rows of the first matrix, and blocks for a second matrix contain respective columns of the second matrix. Results for the data analysis are computed using the blocks of the first and second matrices.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: May 22, 2012
    Assignee: Teradata US, Inc.
    Inventor: Carlos Ordonez
  • Adaptive filtering for bit-depth scalable video codec
    Patent number: 8184693
    Abstract: Adaptive filtering may be used to increase the quality of tone mapped, baseline layer encoded information. As a result, scalable video codecs may be implemented with improved picture quality in some embodiments.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: May 22, 2012
    Assignee: Intel Corporation
    Inventors: Yi-Jen Chiu, Lidong Xu
  • Technique for increasing control and status signal density in a fixed register address space
    Patent number: 8185671
    Abstract: A plurality of registers may function as both the control and status registers. Each bit location of the registers is writable to set a value on a control signal and readable to read a current value on a status signal. A multiplexer provides readability of the current value of each of the registers.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: May 22, 2012
    Assignee: Intel Corporation
    Inventor: Nathan C. Chrisman
  • Enabling speculative state information in a cache coherency protocol
    Patent number: 8185700
    Abstract: In one embodiment, the present invention includes a method for receiving a bus message in a first cache corresponding to a speculative access to a portion of a second cache by a second thread, and dynamically determining in the first cache if an inter-thread dependency exists between the second thread and a first thread associated with the first cache with respect to the portion. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: May 22, 2012
    Assignee: Intel Corporation
    Inventors: Carlos Madriles Gimeno, Carlos García Quinones, Pedro Marcuello, Jesús Sánchez, Fernando Latorre, Antonio González
  • Digital interface and related event manager for integrated circuits
    Patent number: 8184683
    Abstract: In one embodiment, the present invention includes a transceiver coupled to a baseband processor to receive digital control information that includes both event and schedule information, and which stores the digital control information in a storage of the transceiver. The transceiver may then be operated according to the event and schedule information.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: May 22, 2012
    Assignee: Silicon Laboratories Inc.
    Inventors: Brian D. Green, Srihari Adireddy, Lysander Lim, Ramkishore Ganti
  • Well drilling and production using a surface blowout preventer
    Patent number: 8176985
    Abstract: Production and drilling may be achieved by a system which uses a rotating head coupled to surface blowout preventer stack for fluid flow control. A casing connects these surface components to a subsea shutoff assembly with a pair of ram shear devices to cut off the string to the wellhead. Both the casing and an alternate line may be latched so that they may be released if necessary. The rotating head may include a rubber packer to prevent upward flow of drilling fluid and production hydrocarbons and, at the same time, provide rotation to the drill string. Managed pressure drilling or under balanced drilling may be used in some embodiments.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: May 15, 2012
    Assignee: Stena Drilling Ltd.
    Inventor: Gavin Humphreys
  • Filtering of performance monitoring information
    Patent number: 8181185
    Abstract: In one embodiment, the present invention includes a method for receiving a signal in a filter register of a performance monitor from an execution unit to enable a field of the filter register associated with a first thread when a filter enable instruction is executed during execution of code of the first thread, receiving a thread identifier and event information in the performance monitor from the execution unit, and determining if the thread that corresponds to the received thread identifier is enabled in the filter register and if so, storing the event information in a first counter of the performance monitor. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: May 15, 2012
    Assignee: Intel Corporation
    Inventors: Stephen Junkins, Stephen H. Hunt
  • Detection and compensation of discontinuities in data stream
    Patent number: 8179979
    Abstract: In one embodiment of the invention, a method includes receiving a video stream that includes a temporal discontinuity. Checkpoints are distributed in a non-linear fashion with unequal spacing between the checkpoints. The temporal discontinuity is then detected at one of the checkpoints.
    Type: Grant
    Filed: May 1, 2007
    Date of Patent: May 15, 2012
    Assignee: Intel Corporation
    Inventor: Nikolai Shostak
  • Phase change memory that switches between crystalline phases
    Patent number: 8178385
    Abstract: A phase change memory may transition between two crystalline states. In one embodiment, the phase change material is a chalcogenide which transitions between face centered cubic and hexagonal states. Because these states are more stable, they are less prone to drift than the amorphous state conventionally utilized in phase change memories.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: May 15, 2012
    Assignee: Ovonyx, Inc.
    Inventor: Wolodymyr Czubatyj
  • Linking to video information
    Patent number: 8181204
    Abstract: A system enables dynamic linking between a variety of video formats including television broadcasts, web pages, and video displays which are stored on magnetic or optical media. Each frame of the video information is identified together with a plurality of locations within that frame. The locations selected by the user for example using a pointing device is then used to access associated information either within the system itself or on an external system. Thus, in some embodiments of the present invention, any item on a given frame may be linked initially or thereafter to other information within or without the particular system containing that information.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: May 15, 2012
    Assignee: Intel Corporation
    Inventor: Edward O. Clapper