Abstract: In one embodiment of the invention, a pixel unit has two sub-pixel regions each including a liquid crystal capacitor (LCC) and storage capacitor (SC). The capacitance ratio of the SC to LCC of the first sub-pixel differs from the capacitance ratio of the SC to LCC of the second sub-pixel.
Abstract: A technique includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus.
Abstract: An apparatus includes processor and a control interface. The processor is adapted to in a first mode of operation, operate as part of one of a wireless receiver and a wireless transmitter and in a second mode of operation. The processor also processes a first audio band signal to generate a second audio band signal. The control interface selects one of the first and second modes of operation.
Type:
Grant
Filed:
June 29, 2007
Date of Patent:
May 8, 2012
Assignee:
Silicon Laboratories Inc.
Inventors:
G. Tyson Tuttle, Wade R. Gillham, Dan B. Kasha
Abstract: An integrated circuit provides high voltage isolation capabilities. The circuit includes a first area containing a first group of functional circuitry located in a substrate of the integrated circuit. This circuit also includes a second area containing a second group of functional circuitry also contained within the substrate of the integrated circuit. Capacitive isolation circuitry located in the conductive layers in the integrated circuit provide a high voltage isolation link between the first group of functional circuitry and the second group of functional circuitry. The capacitive isolation circuitry distributes a first portion of the high voltage isolation signal across the first group of capacitors in the capacitive isolation circuitry and distributes a second portion of the high voltage isolation circuitry across the second group of capacitors in the capacitive isolation circuitry.
Type:
Grant
Filed:
March 31, 2008
Date of Patent:
May 1, 2012
Assignee:
Silicon Laboratories Inc.
Inventors:
Timothy Dupuis, Axel Thomsen, Zhiwei Dong, Ka Y. Leung
Abstract: In one embodiment, the present invention includes a fabric on a first semiconductor die to communicate with at least one agent on the die according to an on-chip protocol and a packetization layer coupled to the fabric to receive command and data information from the fabric on multiple links and to packetize the information into a packet for transmission from the die to another die via an in-package packetized link. Other embodiments are described and claimed.
Abstract: A technique for managing context state information enables a reduced number of save and restore operations. At least one embodiment includes a plurality of save area segments to store a plurality of machine context state information, which can be saved into the segments and restored to the machine state. One embodiment includes at least one in-use bit vector to indicate status of the plurality of machine context information stored in the segments, and another vector associated with the machine state.
Type:
Grant
Filed:
September 19, 2005
Date of Patent:
May 1, 2012
Assignee:
Intel Corporation
Inventors:
Chris J. Newburn, Dion Rodgers, Bryant E. Bigbee, Shivnandan D. Kaushik, Gautham N. Chinya, Xiang Zou, Hong Wang
Abstract: A directory of a private cache hierarchy is provided to maintain coherency between data stored in the cache hierarchy, where the directory is to enable concurrent cache-to-cache transfer of data to two private caches from another private cache. This directory can be implemented in a system having a multi-core processor. Other embodiments are described.
Type:
Grant
Filed:
December 3, 2008
Date of Patent:
May 1, 2012
Assignee:
Intel Corporation
Inventors:
Christopher J. Hughes, Changkyu Kim, Yen-Kuang Chen
Abstract: In one embodiment, link logic of a multi-chip processor (MCP) formed using multiple processors may interface with a first point-to-point (PtP) link coupled between the MCP and an off-package agent and another PtP link coupled between first and second processors of the MCP, where the on-package PtP link operates at a greater bandwidth than the first PtP link. Other embodiments are described and claimed.
Abstract: Arbitrary, unmodified code and/or software may be executed directly on a host processor operating in a virtualized mode using hardware virtualization support and performance counters. The arbitrary software may be run on the host processor until the host processor exits from the virtualized mode. An end execution time may be calculated in response to the host processor exiting from the virtualized mode. An event may then be handled based on an execution time at which the host processor exited from the virtualized mode and a time at which a scheduled event was to occur.
Type:
Grant
Filed:
April 28, 2006
Date of Patent:
May 1, 2012
Assignee:
Intel Corporation
Inventors:
Magnus Christensson, Samuel Rydh, Magnus Vesterlund, Johan Rydberg
Abstract: Methods and apparatus to perform asynchronous control transfer are described. In one embodiment, upon occurrence of an event (e.g., an architectural event), a service routine data block (SRDB) is accessed via a service routine base pointer (SRDS) and a service routine offset value (SRDBP) to obtain the address of a yield service routine via a service routine instruction pointer (SRIP) and a service routine code segment (SRCS). Other embodiments are also described.
Type:
Grant
Filed:
December 29, 2006
Date of Patent:
May 1, 2012
Assignee:
Intel Corporation
Inventors:
Chris J. Newburn, Dion Rodgers, Robert Knight, Ittai Anati, Aaron N. Levinson, Gautham Chinya
Abstract: Embodiments of an invention for synchronizing redundant processors using state history are disclosed. In one embodiment, an apparatus includes two processors, state storage for each processor, and control logic. Each processor is to execute the same instructions. The state storage is to store compressed processor state information for each instruction executed by the processors. The control logic is to synchronize the two processors based on entries from the state storage.
Type:
Grant
Filed:
December 31, 2008
Date of Patent:
May 1, 2012
Assignee:
Intel Corporation
Inventors:
Shubhendu S. Mukherjee, Arijit Biswas, Paul B. Racunas, Steven E. Raasch
Abstract: Applications may seek access to a radio frequency interface resource on a processor-based system that exceeds the available capacity of that resource. When more than one application needs access to an RF interface resource at the same time and the available capacity of the RF interface resource does not permit all these requests to be granted, contention resolution may be provided. In one embodiment, the contention resolution may involve determining the priority of each application seeking RF interface resource access and granting access based on that priority.
Abstract: Chalcogenide materials conventionally used in chalcogenide memory devices and ovonic threshold switches may exhibit a tendency called drift, wherein threshold voltage or resistance changes with time. By providing a compensating material which exhibits an opposing tendency, the drift may be compensated. The compensating material may be mixed into a chalcogenide, may be layered with chalcogenide, may be provided with a heater, or may be provided as part of an electrode in some embodiments. Both chalcogenide and non-chalcogenide compensating materials may be used.
Abstract: A source-level compiler may randomly select compilation conventions to implement portable content protection, securing the secrets embedded in a program by shuffling associated data. The program may be developed using a source language that is applicative on the associated data. To obscure the embedded secrets, in one embodiment, pre-compiler software may be deployed for compiling the program in a random-execution-order based on a random seed indication that randomly selects compilation conventions and a shuffling algorithm that moves the associated data across the program during execution.
Abstract: In one embodiment, the present invention includes a method for receiving in a processor complex a first write request from a peripheral device, obtaining information of the processor complex responsive to the first write request, and transmitting a second write request from the processor complex to the peripheral device including the information. Other embodiments are described and claimed.
Abstract: Dual gradient drilling may be performed by anchoring drilling tubulars from a drilling ship on the seabed. The drilling tubulars may include an inline pump for pumping mud through another set of tubulars that actually drill the well. Then dual gradient drilling may be instituted by controlling the pressure by controlling the operation of the pump.
Abstract: A processing system to serve as a source device for protected digital content comprises a processor and control logic. When used by the processor, the control logic causes the processing system to generate cipher data, based at least in part on (a) a session key and (b) at least one constant value obtained from a certificate authority. The processing system may use the cipher data to encrypt data, and the processing system may transmit the encrypted data to a receiving device via a wireless connection. Other embodiments are described and claimed.
Abstract: In one embodiment, the present invention includes an apparatus having at least two gain stages to receive incoming signals and to output amplified signals, along with multiple regulators. More specifically, a linear regulator can be coupled to the first gain stage to provide a first regulated voltage to the first gain stage, and a switching regulator coupled to the second gain stage to provide a second regulated voltage to the second gain stage.
Abstract: In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example.
Type:
Grant
Filed:
June 29, 2010
Date of Patent:
April 17, 2012
Assignee:
Intel Corporation
Inventors:
John H. Wilson, Ioannis T. Schoinas, Mazin S. Yousif, Linda J. Rankin, David W. Grawrock, Robert J. Greiner, James A. Sutton, Kushagra Vaid, Willard M. Wiseman
Abstract: A light emitting diode (LED) light source module includes plural voltage converters to convert an input voltage into plural corresponding different operation voltages. A plurality of sets of different color LEDs are provided in the light source module, where each set receives a corresponding one of the operation voltages.