Abstract: A telestrator system is disclosed that allows a broadcaster to annotate video during or after an event. For example, while televising a sporting event, an announcer (or other user) can use the present invention to draw over the video of the event to highlight one or more actions, features, etc. In one embodiment, when the announcer draws over the video, it appears that the announcer is drawing on the field or location of the event. Such an appearance can be performed by mapping the pixels location from the user's drawing to three dimensional locations at the event. Other embodiments include drawing on the video without obscuring persons and/or other specified objects, and/or smoothing the drawings in real time.

Abstract: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

Abstract: A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link.

Abstract: An integrated circuit buffer device including a first port and a second port. The first port to receive data from a first integrated circuit memory device, and the second port to receive data from a second integrated circuit memory device. The integrated circuit buffer device further includes a multiplexer to output a data stream that includes the data received from the first integrated circuit memory device and the data received from the second integrated circuit memory device. In addition, the integrated circuit buffer device includes an interface including transmit circuitry to transmit the data stream to an integrated circuit controller device.

Abstract: A system, a wireless hand-held device, and software component for accessing information responsive to short-range radio signals is provided. The system includes a wireless gateway device coupled to a network, such as a cellular network. The wireless gateway device includes a network manager software component for accessing information from the network responsive to a first short-range radio signal. The network may be a corporate, private or public network, such as the Internet. A first wireless device is coupled to the wireless gateway device. The first wireless device provides the first short-range radio signal. In an embodiment of the present invention, the first wireless device is a cellular telephone, personal digital assistant or thin terminal having a Bluetooth™ processor and transmitter. In an embodiment of the present invention, the network manager software component includes a plug and play software component for loading and executing software for the first wireless device.

Abstract: An electronic educational toy having a housing for teaching children comprising a toy housing supporting a substantially planar work platform on which a child can make selections by causing contact with the work platform and enclosing a speaker, a processor, and a sensing system sensing occurrences of contact caused by the child across the surface of the work platform.

Abstract: A system is disclosed for programming non-volatile memory with greater precision. In one embodiment, the system includes applying a first phase of a boosting signal to one or more unselected word lines for a set of NAND strings, applying a programming level to selected bit lines of the NAND strings while applying the first phase of the boosting signal, and applying an inhibit level to unselected bit lines of the NAND strings while applying the first phase of the boosting signal. Subsequently, a second phase of the boosting signal is applied to the one or more unselected word lines and the signal(s) on the selected bit lines are changed by applying the inhibit level to the selected bit lines so that NAND strings associated with the selected bit lines will be boosted by the second phase of the boosting signal. A program voltage signal is applied to a selected word line in order to program storage elements connected to the selected word line.

Abstract: Check valves including components having a straightforward and simple design allowing the components to be scaled down to an extremely small size without losing functionality or performance of the check valve.

Abstract: The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elements reaches a certain verify level, after which a defined maximum number of additional pulses may be applied to other memory elements to allow them to also reach associated target threshold voltage levels. The technique enforces a maximum allowable number of programming pulses that can change over time as the memory is cycled.

Abstract: Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are different than a corresponding level used to program other cells or word lines. One exemplary embodiment includes using a lower threshold voltage verify level for select physical states when programming the last word line to be programmed for a string during a program operation. Another embodiment includes applying a lower program voltage to program memory cells of the last word line to select physical states. Additional read levels are established for reading the states programmed using lower verify levels in some exemplary implementations.

Abstract: In a system for programming non-volatile storage, technology is disclosed for programming with greater precision and reasonable program times. In one embodiment, a first voltage is applied to a bit line for a first non-volatile storage element in order to inhibit that first non-volatile storage element. A first program voltage is applied to the first non-volatile storage element. For example, a program pulse is applied to a control gate for the first non-volatile storage element. During the program pulse, the bit line is changed from said first voltage to a second voltage, where the second voltage allows the first non-volatile storage element to be programmed.

Abstract: An electronic educational toy having a housing for teaching letters, words, numbers or pictures comprising a toy housing supporting a substantially planar work platform on which a child can make selections by causing contact with the work platform and enclosing a speaker, a processor, and a sensing system sensing occurrences of contact caused by the child across the surface of the work platform.

Abstract: A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link.

Abstract: An optical fiber connector comprising a main body in the form of a manipulator 11 having a throughbore which removably receives a sleeve-like carrier 13 again having a throughbore. The carrier 13 receives removably an optical fibre assembly which is to be coupled to another optical component by means of the connector. The manipulator 11 also includes two pairs of adjustment screws 18a, and 19a which can be used to displace the carrier and optical fibre assembly relative to the longitudinal axis of the manipulator. A polarising element 41 is arranged in the manipulator 11 such that light passing through the connector system will pass through the polarising element 41.

Abstract: A method, system, and computer readable medium allows downloading of a software component to a short distance wireless network in response to device information and/or user information. In an embodiment of the present invention, the device information includes type of device, manufacturer of device, where purchased, when activated in the short distance wireless network. In an embodiment of the present invention, user information includes a user preference, price plan, usage, promotional plan and/or replacement plan. In an embodiment of the present invention, device information is included in a short-range radio signal generated from the device to a cellular device. In an embodiment of the present invention, software components are downloaded from a processing device in a Wide Area Network (WAN) coupled to the short distance wireless network.

Abstract: A device, method, system and computer readable medium allows for a fast recovery of a communication connection in response to a newly assigned Wide Area Network (“WAN”) Internet protocol (“IP”) source address. In an embodiment of the present invention, a device provides communication between a WAN and a short distance wireless network. The device comprises a memory to store a first and a second WAN address for the device and a router software component. The processor and router software component transfers a first plurality of packets between the device and the wide area network using the first wide area network address. The processor and router software component discontinues the transfer of the first plurality of packets responsive to receiving the second wide area network address and transfers a second plurality of packets between the device and the wide area network using the second wide area network address.

Abstract: A method, system, and computer readable medium allows a short distance wireless network or networks to provide information to a telecommunication server, or other third party processing device, in order to make a business decision according to embodiments of the present invention. In embodiments of the present invention, the information is 1) wide area network telecommunication usage of a device in the short distance wireless network, 2) the device health, 3) the battery health of the device. In an embodiment of the present invention, the business decision includes 1) generating an invoice based on the type and manufacturer of device accessing the telecommunication network, the type and period of time of data transferred, 2) providing a replacement device 3) providing a replacement battery, 4) downloading a software component to the device for added service, 5) providing a pricing plan, 6) providing a promotional plan or 7) changing a rate schedule.

Abstract: The present invention is an input/output (I/O) structure for an integrated circuit device which increases the input signal energy transfer characteristic and allows for increased operating frequency of the device. The I/O structure includes a conductive region in a doped region below a semiconductor bond pad. The I/O structure also includes a tapped region coupled to a supply voltage. The I/O structure may also include an output driver transistor layout with a tapped source region to decrease a parasitic series resistance between a drain region and a source voltage.

Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

Abstract: A socket (14) includes a first bus conductor (22a) having two or more contact regions (24) and a second bus conductor (22b) arranged substantially parallel to the first bus conductor and having two or more contact regions (24). The first and second bus conductors are spaced relative to one another so as to provide a predetermined electrical impedance and may be arranged to carry electrical signals as transmission lines. A dielectric spacer (36) may be disposed between the first and second bus conductors to provide the spacing. Contact regions (24) of the first and second conductors (22a, 22b) may provide compliant coupling regions for the socket (14). The contact regions (24) of the first bus conductor (22a) may be positioned within the socket (14) so as to contact a lead disposed on a first side of a circuit element (16) and the contact regions (24) of the second bus conductor (22b) may be positioned within the socket (14) so as to contact the lead disposed on the second side of the circuit element (16).