Abstract: A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems.

Abstract: An I/O circuit disposed on an integrated circuit substrate and having reduced parasitic capacitance. The I/O circuit includes a signal line segmented into a first signal line segment and a second signal line segment, and an inductive structure disposed between the first and second signal line segments. An on-chip termination element is coupled to the first signal line segment, and an electrostatic discharge (ESD) element is coupled to the second signal line segment.

Abstract: In one aspect, an application object for a synchronization system is provided on a network coupled processing device. The application object may comprise a plurality of objects, each object translating third party data to a universal middle format, including a root object providing an entry point into individual application databases; and at least one child object; and at least one interface object. In another aspect, an application object is provided on a server coupled to a network. In this aspect, the application object may comprise an application data function call interpreter, the interpreter being accessible to a synchronization engine and an application running on a network coupled device having user data; and a universal data record mapping formatter.

Abstract: The end face of an optical fiber 11 is polished at an angle to alter the cross-sectional dimensions of a light beam exiting the fiber through that end face to alter the cross-sectional circularity of the light beam after it has exited the fiber as compared to its cross-sectional circularity when it is in the fiber. For example, to increase the circularity of an exiting light beam, the angled fiber end face can be aligned such that the major axis of the sloping fiber end face is aligned with the major cross-sectional axis of the light beam in the fiber (i.e. perpendicular to the minor cross-sectional axis of the light beam in the fiber). This has the effect of reducing the length of the major cross-sectional axis of the light beam once it has exited the fiber.

Abstract: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

Abstract: A computer system includes a controller device having an interface disposed on a circuit board. A first socket is disposed on the circuit board and receives a first memory module having a first integrated circuit buffer device. The first memory module has a first plurality of integrated circuit memory devices coupled to the first integrated circuit buffer device. A first point-to-point link is coupled to the interface of the controller device. When the first memory module is received by the first socket, the first integrated circuit buffer device receives control information, address information, and data from the controller device over the first point-to-point link. A second socket is disposed on the circuit board and receives a second memory module having a second integrated circuit buffer device. The second memory module has a second plurality of memory devices coupled to the second integrated circuit buffer device.

Abstract: A circuit, apparatus and method for efficiently and accurately calibrating an output driver current are provided in embodiments of the present invention. In an embodiment of the present invention, a circuit comprises a first digital-to-analog converter (“DAC”) that generates a first current. A first transistor is coupled to the first DAC and generates a first biasing current responsive to the first current. A second DAC is coupled to the first transistor and generates a first control current responsive to the first biasing current. According to an embodiment of the present invention, the first and second DACs are binary weighted control DACs. According to an embodiment of the present invention, the binary weighted values of the second DAC are obtained in response to a calibration signal generated by a controller. According to an embodiment of the present invention, the first DAC is an M-bit DAC and the second DAC is an N-bit DAC, wherein M is less than N.

Abstract: A system comprises a master device and a first integrated circuit buffer device. A first plurality of integrated circuit memory devices are coupled to the first integrated circuit buffer device. A first plurality of signal lines are coupled to the first integrated circuit buffer device and the master device, wherein the first plurality of signal lines communicate control information, address information and data from the master device to the first integrated circuit buffer device. A second plurality of signal lines are coupled to the first integrated circuit buffer device. A second integrated circuit buffer device is coupled to the second plurality of signal lines, the second integrated circuit buffer device receives the control information, the address information and the data from the first integrated circuit buffer device over the second plurality of signal lines. A second plurality of integrated circuit memory devices are coupled to the second integrated circuit buffer device.

Abstract: A circuit, apparatus and method provides a lock state value representing an amount of time a phase alignment circuit (“PAC”), such as a PLL or DLL, is tracking or locked to an incoming reference signal for a predetermined period of time. In an embodiment of the present invention, a lock state detection circuit is coupled to a lock loop circuit and includes a phase detection circuit and a counter circuit. The phase detection circuit includes a phase detector and delay elements that are coupled to the PAC phase detector. The phase detector outputs a lock state sample value of the PAC. In an embodiment of the present invention, the PAC is locked when a stream of alternating lock state sample values, logical 1's and 0's, are output from the phase detector. The counter circuit includes a flip-flop, an XOR gate and counter for obtaining a lock state value for a predetermined period of time.

Abstract: A system for dissipating static electric charge from electronics on a circuit board as the board is inserted into the enclosure, the system comprising one or more elastic, deformable and electrically conductive gaskets mounted within the enclosure for engaging ground pins on the circuit board.

Abstract: A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a corresponding one of the driver circuits. Each of the select circuits includes a control input to receive a respective select signal and a plurality of data inputs to receive a plurality of data signals. Each of the select circuits is adapted to select, according to the respective select signal, one of the plurality of data signals to be output to the control input of the corresponding one of the driver circuits.

Abstract: A method of operating a memory system that includes an integrated circuit memory device is provided. A value representing an output voltage setting of an output driver of the memory device is stored in a register. The output driver outputs the drive voltage. A signal derived from the drive voltage is compared to a reference signal to generate a signal that indicates an adjustment to the output voltage setting. The output voltage setting of the output driver is adjusted using a counter that holds a count value representing an update to the output voltage setting. The count value is updated in accordance with a signal that indicates the adjustment to the output voltage setting.

Abstract: A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e.g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.

Abstract: A system in accordance with an embodiment of the invention provides Quality of Service (QoS) for Storage Access. Such QoS is partially enabled in one embodiment by the automatic pooling of storage devices and provisioning virtual targets from those pools. QoS is enforced in one embodiment by keeping the bandwidth for each connection within a specified range, and particularly, by controlling the number of allowed concurrent requests from an initiator. Load balancing is also provided in one embodiment, improving response times for requests, further easing the ability to provide QoS.

Abstract: A system including an integrated circuit memory device. The integrated circuit device comprises a register to store a value representative of an output voltage setting. A circuit holds a value representative of an adjustment to the output voltage setting. An output driver outputs a drive voltage during a calibration operation, wherein a signal is generated based on a comparison between a signal derived from the drive voltage and a reference voltage. The signal updates the value representative of the adjustment to the output voltage setting.

Abstract: A method and apparatus for creating a memory model for use in modeling a physical memory of an electronic circuit design. Memory write operations to the physical memory and memory read operations are modeled in a lookup table. The number of entries in the lookup table is limited by an upper bound representing a total number of memory operations that can occur over a given number of clock cycles.

Abstract: A system is disclosed for using camera attitude sensors with a camera. A camera assembly includes a tripod base, a tripod head interface mounted on the tripod base, a tripod head mounted on the tripod head interface and a camera mounted on the tripod head. The tripod head enables the camera to pan and tilt. The system also includes a first optical encoder for detecting the amount that the camera has been panned and a second optical encoder for detecting the amount that the camera has been tilted. Two inclinometers are mounted on the tripod head interface to measure attitude of the tripod head. Two gyroscopes (“gyros”) are mounted on the camera assembly. Data from the encoders, gyros and inclinometers are packaged and sent to graphics production equipment to be used for enhancing video captured by the camera.

Abstract: A screwdriver for driving collated screws including a slide body coupled to a housing for reciprocal displacement in a cycle including a retraction stroke and an extension stroke. A lever pivotably mounted to the slide body carries at one end a cam pin received in a cam slot in the housing with the other end of the lever advancing successive screws in the screwstrip, the cam slot having first and second camming surfaces for selective engagement by the cam pin to vary the relative positionning of the lever to be different for the same position if the slide body in the housing in the retraction strokes than in the extension stroke.

Abstract: An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count value indicating a phase difference between a reference clock signal and a first plurality of clock signals. The phase mixer combines the first plurality of clock signals in accordance with the sum of the selected offset and the phase count value to generate an output clock signal.

Abstract: An interface engine provides animated views in a user interface. The interface engine directs the operation of a rendering environment to create an interface in a rendering area. The interface engine includes views, layouts, animators, and constraints. Views identify child views and resources for display in the rendering area. In response to events, such as user inputs, a view modifies itself by calling layouts, animators, and constraints. A layout manages the attributes of a view's child views, including child view position and size. An animator modifies the view's appearance over a specified period of time. A constraint imposes limits on view properties. In one implementation, an Internet site delivers an interface engine to a browser to supply content and a user interface. A presentation server compiles an interface engine description and specified resources into an interface engine.