Abstract: An integrated circuit device having a select circuit, a summing circuit and a phase mixer. The select circuit selects one of a plurality of offset values as a selected offset. The summing circuit sums the selected offset with a phase count value, the phase count value indicating a phase difference between a reference clock signal and a first plurality of clock signals. The phase mixer combines the first plurality of clock signals in accordance with the sum of the selected offset and the phase count value to generate an output clock signal.

Abstract: A system uses GPS receivers and other sensors to acquire data about one or more objects at an event. The data acquired by the GPS receivers and the sensors is used to determine various statistics about the objects and/or enhance a video presentation of the objects. In one embodiment, the acquired data is used to determine three dimensional positions of the objects, determine the positions of images of the objects in a video and enhance the video accordingly. One exemplar use of the present invention is with a system for tracking automobiles at a race. The system determines statistics about the automobiles and enhances a video presentation of the race.

Abstract: A data package containing instructions for manipulating user data. The package includes a header identifying the data package and containing information on content in the data package; transaction objects operable to effect a change to user data; and object operation instructions. The objects can be binary data or structured data. A grouping of data packages can contain changes for a user's data across multiple systems.

Abstract: Described herein is a biopsy needle comprising a hollow outer tube at the end of which is a rectangular opening having sharpened edges. In preferred embodiments, the needle has one lumen formed by the needle or two lumens, formed either by a second hollow member positioned within the needle, or a ------- semi-circular tube inserted within the needle. To remove tissue using the needle, one inserts it into a patient's body, applies suction to the single or double lumens and then rotates the needle. Tissue is drawn into the needle lumen for subsequent evaluation by a Pathologist.

Abstract: A track model is created for use with a GPS receiver. In one embodiment, the track model is a set of planar surfaces which approximate the contiguous surface on which navigation takes place. The GPS receiver searches for an appropriate planar surface associated with its approximate position. Having found the appropriate planar surface, the GPS receiver constrains its position using the planar surface associated with its approximate position. Using the track model improves the accuracy of the computed position at the time and improves the ambiguity estimation process so that positions with greatly improved accuracy are available sooner.

Abstract: An apparatus and method for producing a diffusive, continuous laminar flow for particle growth via condensation of vapors with a mass diffusivity near or higher than the thermal diffusivity of the surrounding gas. In an exemplary embodiment, the method uses the condensation of water vapor onto particles suspended in air.

Abstract: A microfabricated device includes a substrate having a device layer and substantially filled, isolating trenches; a doped region of material formed by photolithographically defining a region for selective doping of said device layer, selectively doping said region, and thermally diffusing said dopant; circuits on said device layer formed using a substantially standard circuit technology; and at least one structure trench in the substrate which completes the definition of electrically isolated micromechanical structural elements.

Abstract: An integrated circuit device having a self-resetting phase-locked loop (PLL) circuit. The PLL circuit generates an output clock signal having a first frequency in a first operating mode and a second frequency in a second operating mode, the second frequency being determined, at least in part, by a reference clock signal. A control circuit within the integrated circuit resets the PLL circuit by selecting the first operating mode for a predetermined time interval, then selecting the second operating mode.

Abstract: A system in a processing device having at least one application including application data in a format in an application data store. The system includes: a system data store associated with the processing device including a representation of a previous state of application data in the application data store; a difference engine generating difference information associated with a change to said application data store; and an application interface, interpreting application data for the difference engine. The difference engine may further comprise a delta engine comparing the change to said application data store to said system data store to construct difference information. In a further aspect, a method for updating data files in a first system is provided.

Abstract: A semiconductor memory device that includes an array of memory cells, the memory device operating synchronously with respect to an external clock signal. The memory device includes a set of interface terminals to receive a plurality of control signals which specify that the memory device receive a first set of data bits and a second set of data bits. The first set of data bits are received during a first half of a first clock cycle of the external clock signal. The second set of data bits are received during a second half of the first clock cycle of the external clock signal. In addition, the memory device includes a mask terminal to receive first and second mask bits during a second clock cycle of the external clock signal. The first clock cycle is temporally offset from the second clock cycle. The first mask bit is received during a first half of the second clock cycle, the first mask bit to indicate whether to write the first set of data bits to the array.

Abstract: A circuit, apparatus and method for efficiently and accurately calibrating an output driver current are provided in embodiments of the present invention. In an embodiment of the present invention, a circuit comprises a first digital-to-analog converter (“DAC”) that generates a first current. A first transistor is coupled to the first DAC and generates a first biasing current responsive to the first current. A second DAC is coupled to the first transistor and generates a first control current responsive to the first biasing current. According to an embodiment of the present invention, the first and second DACs are binary weighted control DACs. According to an embodiment of the present invention, the binary weighted values of the second DAC are obtained in response to a calibration signal generated by a controller. According to an embodiment of the present invention, the first DAC is an M-bit DAC and the second DAC is an N-bit DAC, wherein M is less than N.

Abstract: A request, such as those embedded in URLs and XML documents, is assigned to a thread of execution in a server that is in communication with a data store. The thread of execution includes a thread local storage with a pointer to a cache object. The cache object maintains copies of data store entries frequently accessed by the assigned request. The cache object is accessed in response to data store access commands arising from the request. When a data store access command specifies a data store entry not found in the cache object, the server creates and loads a corresponding cache object entry. The cache object is not updated when other requests alter data store entries, and memory access commands arising from other requests cannot cause the cache object to be accessed. When the request causes the server to write data to the data store, the cache object also maintains a copy of the written data.

Abstract: A system and method for synchronizing devices which can couple to the Internet, or any network. The system includes a first sync engine on the first system interfacing with data on the first system to provide difference information. A data store is coupled to the network and in communication with the first and second systems. A second sync engine is provided on the second system coupled to receive the difference information from the data store via the network, and interface with data on the second system to update said data on the second system with said difference information. Difference information is transmitted to the data store by the first sync engine and received from the data store from the second sync engine.

Abstract: A method and apparatus for testing DRAM is described. The method and apparatus causes the DRAM pins to be reconfigured to provide a direct path between the memory core and the DRAM pins. This reconfiguration allows the memory core to be “seen” without probing and also allows faster and simpler testing with a more traditional protocol. The method and apparatus for testing also provides for several options to further increase testing speed. These options include an internal block compare and a core noise option. The internal block compare performs an internal parallel bit by bit comparison of read data to the contents of a write buffer and generates an error signal if a mismatch occurs. The core noise option simulates the noise that can occur during the normal mode of operation that does not occur during testing.

Abstract: A device for dispensing units of platform-loaded goods from a stack is provided which comprises a dispenser including a dispenser frame, capture blades, and a blade control. The capture blades retain the stack within the dispenser when in closed position and release the stack when in open position, and the blade control opens and closes the capture blades. The device also includes a device for engaging the dispenser such that the blade control is moved upwardly in relation to the dispenser frame to open said capture blades.

Abstract: Progressively optimized clock tree/mesh construction is performed concurrently with placement of all remaining objects. Clock tree/mesh is specified loosely for initial placement, then followed by progressive detailed placement. In particular, preferred approach provides automated and reliable solution to clock tree/mesh construction, occuring concurrently with placement process so that clock tree wiring and buffering considers and influences placement and wiring of all other objects, such as logic gates, memory elements, macrocells, etc. Hence, in this concurrent manner, clock tree/mesh pre-wiring and pre-buffering may be based on construction of approximate clock tree using partitioning information only, i.e., prior to object placement. Further, present approach provides modified DME-based clock tree topology construction without meandering, and recursive algorithm for buffered clock tree construction.

Abstract: A duty cycle correction circuit operates by alternately speeding and slowing successive transitions of an input clock signal. By altering the rising and falling edge rates of a clock signal asymmetrically, the duty cycle of the clock signal is adjusted without shifting the DC level of the clock signal. In one embodiment, the duty cycle correction circuit includes current sources in place of resistive loads to avoid shifting the DC level of output clock signals. Frequency-dependent current sources that generate increased bias currents at higher frequency are used to achieve duty cycle correction over a broad range of input frequencies.

Abstract: A pool cleaner includes a cleaning body adapted to be coupled to a suction source, a foot pad assembly coupled to the elongate member, and at least one deflection member coupled to the foot pad assembly by an adjustable coupling. The deflection member may be configured both horizontally and vertically relative to the cleaning body.