Abstract: A voltage translator circuit capable of operating at high speed, saving the power consumption, and forming to have a smaller circuit area. When the output level of a decoder 110 is changed from the potential GND to the potential VDD, a pMOS transistor 125 is turned off, and the gate of nMOS transistor 124 comes to have a high impedance. Because of this, the self-boost effect acts on the gate of the nMOS transistor 124 to push up the source potential of the nMOS transistor 124. Consequently, the gate potential of the pMOS transistor 122 is abruptly raised, and this pMOS transistor 122 is turned off at high speed. The pMOS transistor 122 being turned off at high speed, the penetration current flowing through the transistors 121 and 122 is reduced and the electric potential of the word line WL falls at high speed.
Abstract: A conductive layer which is formed on an insulative layer on a semiconductor substrate is connected to the semiconductor substrate via a through portion which passes through the insulative layer and reaches the semiconductor substrate. In a state where the conductive layer is electrically connected to the semiconductor substrate via the through portion, a patterning process using a plasma etching is performed on the conductive layer, thereby forming a conductive path. After the formation of the conductive path, a heating process is performed on the substrate or the conductive path in order to disconnect the electrical connection between the through portion and the substrate by a reaction between the through portion and the semiconductor substrate which is in contact therewith.
Abstract: An ion generator generates ions above a semiconductor wafer and the ions are directed towards a surface of a semiconductor wafer. The ions combine with static charges on the semiconductor wafer to thereby discharge the surface of the semiconductor wafer.
Abstract: There is disclosed a method for forming an interconnection in the semiconductor element, including a process for forming a groove 117 on an underlying substrate so as to correspond to the designed pattern, a process for forming an underlayer to improve crystalline of an interconnection which will be formed in the succeeding stage on said underlying substrate with said groove, a process for forming a thin film of the interconnection material, a heat-treatment process to fill the said groove with the thin film of the interconnection material formed on the underlying substrate, and a process for forming the interconnection by polishing the surface of the thin film by predetermined quantity.
Abstract: The photosensitive polymer includes a first monomer which is norbornene ester having C1 to C12 aliphatic alcohol as a substituent, and a second monomer which is maleic anhydride. A chemically amplified photoresist composition, containing the photosensitive polymer, has an improved etching resistance and adhesion to underlying layer materials, and exhibits wettability to developing solutions.
March 10, 2003
Date of Patent:
May 17, 2005
Samsung Electronics Co., Ltd.
Dong-won Jung, Sang-jun Choi, Si-hyeung Lee, Sook Lee
Abstract: A polishing pad conditioner for a chemical-mechanical polishing apparatus includes a conditioning plate having a first recess and a holder having a second recess. The first recess is formed on the upper face of the conditioning plate, and the second recess is formed on the bottom face of the holder. A first filling member having a specific gravity smaller than that of the conditioning plate fills up the first recess, and a second filling member having a specific gravity smaller than that of the holder fills up the second recess. Therefore, the weight of the polishing pad conditioner can be reduced, and the durability and service life of an air bladder that adjusts the height of the polishing pad conditioner can be improved.
Abstract: A power supply control circuit includes a comparator which compares the supply voltage (VDDV) with a predetermined reference voltage (VREF) and supplies a comparison signal (CMP) when the supply voltage (VDDV) reaches the reference voltage (VREF); and a controller which initiates wake-up operation of the circuit block in accordance with the comparison signal (CMP) of the comparator.
Abstract: A method for fabricating a semiconductor device and forming an insulating film used therein, includes forming an isolation insulating film on a semiconductor wafer and forming gates, separated by gaps having a predetermined distance, on an active region. Next, a first interlayer dielectric film is deposited to a predetermined thickness on the semiconductor wafer having the gates, so that the gaps between the gates are not completely filled. Then, a sputtering etch is performed entirely on a surface of the first interlayer dielectric film. Thereafter, the first interlayer dielectric film is partially removed through isotropic etching. Next, a second interlayer dielectric film is deposited on the first interlayer dielectric film so that the gaps between the gates are completely filled.
Abstract: A ferroelectric memory reads data from a memory cell by using a sense amplifier to compare a reference potential with a potential produced on a bit line by the memory cell. The reference potential may generated by a pre-charge circuit connected to the sense amplifier. Alternatively, the reference potential may be generated by the memory cell itself. In either case, the reference potential is obtained without the need for a reference cell, and without the need to drive a bit line to the reference potential. Current consumption is accordingly reduced, and integration density can be increased.
Abstract: A polishing slurry including an abrasive, deionized water, a pH controlling agent, and polyethylene imine, can control the removal rates of a silicon oxide layer and a silicon nitride layer which are simultaneously exposed during chemical mechanical polishing (CMP) of a conductive layer. A relative ratio of the removal rate of the silicon oxide layer to that of the silicon nitride layer can be controlled by controlling an amount of the choline derivative.
Abstract: A system and method automatically analyzes and manages loss factor data of test processes in which a great number of IC devices are tested as a lot with a number of testers. The lot contains a predetermined number of identical IC devices, and the lot test process is performed sequentially according to a predetermined number of test cycles. The system include a means for verifying test results for each of the test cycles and for determining whether or not a re-test is to be performed and an IC device loading/unloading means for loading IC devices to be tested and contained in the lot to a test head and for unloading the tested IC devices from the test head by sorting the tested IC devices according to the test results.
October 9, 2001
Date of Patent:
February 15, 2005
Samsung Electronics Co., Ltd.
Kyu Sung Lee, Ae Yong Chung, Sung Ok Kim
Abstract: A method of fabricating a semiconductor device according to the invention comprises forming a capacitor comprising a lower electrode formed on a semiconductor substrate, a capacitive insulator made up of a metal oxide film, formed on the lower electrode, and an upper electrode formed on the capacitive insulator; forming a metal pattern to be electrically connected to the electrodes of the capacitor; forming a first protection film which coats at least a side face of the metal pattern; and forming a water constituents diffusion preventive film on the side face and top face of the metal pattern through the intermediary of the first protection film. As a result, a method of fabricating a ferroelectric memory capable of protecting a ferroelectric capacitor from water constituents evolved during a fabrication process, and maintaining satisfactory memory characteristics can be provided.
Abstract: A semiconductor device includes a low dielectric constant insulating film exhibiting an Si—H Fourier Transform Infrared (FTIR) doublet defined by a first and a second peak, wherein the first peak is located at a higher wave number than the second peak, and wherein the ratio of the first peak to the second peak is greater than unity. A method of producing such a semiconductor device includes depositing a dielectric layer over a substrate and treating the dielectric layer in a hydrogen containing plasma such that the dielectric layer exhibits an Si—H Fourier Transform Infrared (FTIR) doublet defined by a first and a second peak, wherein the first peak is located at a higher wave number than the second peak, and wherein the ratio of the first peak to the second peak is greater than unity.
Abstract: A structure having trench isolation which protects a nitride liner in the trench during subsequent plasma processing. The structure includes a trench formed in a semiconductor substrate, the trench having sidewalls and a bottom. A thermal oxide layer is formed on the bottom and sidewalls of the trench so as to remove substrate damage caused during etching of the semiconductor substrate to form the trench. A material layer is formed on the thermal oxide layer so as to prevent the bottom and sidewalls of the trench from being oxidized. Then, a protection layer is formed on the oxidation barrier layer. The trench is filled with a trench fill material uniformly with respect to the bottom and sidewalls of the trench.
September 10, 2001
Date of Patent:
January 18, 2005
Samsung Electronics Co., Ltd.
Young-woo Park, Yong-chul Oh, Won-Seong Lee
Abstract: The present invention provides a method and a system for generating a phase-modulated wave front. According to the present invention, the spatial phase-modulation is not performed on the different parts of the wave front individually as in known POSLMs. Rather, the spatial phase-modulation of the present invention is performed by generating an amplitude modulation in the wave front, Fourier or Fresnel transforming the amplitude modulated wave front, filtering Fourier or Fresnel components of the Fourier or Fresnel distribution with a spatial filter such as a phase contrast filter, and regenerating the wave front whereby the initial amplitude modulation has transformed into a phase-modulation.
Abstract: A buried gate electrode of a buried MOS transistor formed within a trench in an active region wherein a gate oxide film and a gate electrode are buried in the trench, and a lower electrode of a PIP capacitor formed on a device isolation, are simultaneously formed by etching of polycrystalline silicon formed on an entire surface of the structure.
Abstract: A field oxide film for element isolation is formed on an SOI substrate having a silicon layer formed on an insulating layer, an active nitride film is wet-etched to reduce its film thickness to a value small enough to allow the edge of the silicon layer to become exposed and ions of a channel stopping impurity are implanted only into the edge of the silicon layer through self-alignment either vertically or at an angle by using the active nitride film as a mask. Through this manufacturing method, a field effect transistor which achieves a small gate length, is free from the adverse effect of a parasitic transistor and thus does not readily manifest a hump, and allows a reduction in the distance between an nMOS and a pMOS provided next to each other is realized.
Abstract: A method of manufacturing a capacitor includes sequentially forming a storage electrode, a high dielectric layer, a plate electrode, and an interdielectric layer over a semiconductor substrate. A first post-annealing of the substrate is performed under an inert atmosphere at a first temperature, and then a second post-annealing is performed at a second temperature. The first and second post annealings can be performed after forming the high dielectric layer, the plate electrode, or the interdielectric layer, or any combination thereof, as long as the second post-annealing is performed after the first post-annealing. The post-annealings are not necessarily performed in a same place or stage. The first temperature may be about 600° C. to 900° C., and the second temperature about 100° C. to 600° C. As a result, the dielectric constant of the high dielectric layer is increased, and leakage current is reduced.
Abstract: A field effect transistor comprises a silicon layer formed on an insulator, a diffused layer formed by diffusing dopant from a part of a surface of the silicon layer up to the insulator, a silicide layer formed toward the insulator side from a surface of the diffused layer so as to have a thickness less than or equal to that of the diffused layer, a contact conductive layer formed on the surface of the silicide layer, a gate insulating layer formed on the silicon layer, a gate electrode formed on the gate insulating layer and a sidewall formed on a side surface of the gate electrode. The shortest distance X between surfaces opposed to each other, of the contact conductive layer and the sidewall satisfies a relation represented by the following expression (1):
Abstract: A silicon-on-insulator (SOI) substrate is provided which includes a silicon substrate having an upper surface, a first insulating layer having a lower surface extending horizontally over the upper surface of the silicon substrate, and a silicon layer having a lower surface extending horizontally over an upper surface of the first insulating layer. A second insulating layer is formed over an upper surface of the silicon layer of the SOI substrate. Impurity ions are implanted into the silicon layer of the SOI substrate such that a peak ion concentration along a vertical depth of the silicon layer is located between an intermediate horizontal plane of the silicon layer and the lower surface of the silicon layer inclusive, wherein the intermediate horizontal plane extends horizontally within the silicon layer at half a vertical depth of the silicon layer. A gate electrode is formed on the second insulating layer.