Abstract: An address selection circuit in a synchronous memory device receives a clock signal and an address signal, passes the received address signal asynchronously from an address input circuit to an address decoder to generate an address selection signal, then uses the same received address signal to generate further address selection signals in synchronization with the clock signal. This scheme enables the address selection signals to be generated more quickly than if all address signal paths were synchronized with the clock signal. In a burst access, even the first address selection signal can be generated relatively quickly.

Abstract: A first operational amplifier receives a reference voltage at one input terminal, a first transistor is connected between a first power source line and the first operational amplifier, a second transistor is connected between the first power source line and the first operational amplifier, a resistor is connected between the first transistor and a second power source line, a first switch is connected to the second transistor, a variable capacitor connected between the first switch and the second power source line, a second switch is connected the variable capacitor and the second power source line, a second operational amplifier is connected to the variable capacitor and the reference voltage, a third switch is connected to the second transistor, a load is connected between the third switch and the second power source line, and a control circuit is connected to the first to third switches.

Abstract: A method of manufacturing a mask ROM for storing quaternary data enables short turn around time, makes refining cell sizes simple, and enables stable reading of data. Gaps are formed between word lines in the memory cell transistors and two diffusion areas. Impurities are doped into these gaps in accordance with quaternary write data when data is written. A current runs between these diffusion areas only when one of these two areas into which impurities have been doped is used as a drain. Accordingly, quaternary data can be read by a first reading when the first diffusion area is a source and the other diffusion area is a drain, and by reading a second reading when the first diffusion area is used as a drain and the other diffusion area as a source.

Abstract: A method of analyzing a composition depth profile of a solid surface layer, wherein actually-measured intensity of photoelectrons emitted from the solid surface layer by irradiating the solid surface layer containing at least two or more species of element with X rays and photoelectron calculated intensity obtained by making a calculation assuming an elemental composition ratio for each of a plurality of sub-layers into which the solid surface layer has been temporarily divided are utilized to determine a composition depth profile of the solid surface layer, the method including a step of at least repeating an approximate calculation including: distinguishing a specified sub-layer such that the calculated intensity best converges to the actually-measured intensity in the sub-layers; and correcting an elemental composition ratio at least for the specified sub-layer so that the calculated intensity converges to the actually-measured intensity, thereby determining the composition depth profile of the solid surfa

Abstract: A method of removing photoresist from a wafer or other substrate consists of ashing the photoresist only once the wafer is spaced a predetermined distance above a wafer stage in a process chamber, so that the photoresist is removed at once from all of the surfaces of the wafer. The wafer is heated to a temperature of 210° C. to 230° C. after it is positioned on the upper surface of the wafer stage. The heated wafer is then raised a distance of 9 mm to 11 mm above the upper surface of the wafer stage. At this time, process gas is introduced into the process chamber, and the process gas is converted into plasma. Thus, the plasma efficiently removes the photoresist all at once from the surfaces of the wafer.

Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate, forming an insulating film having a opening, forming a titanium film so as to extend from the semiconductor substrate in the opening to the insulating film surface, plasma treating the titanium film with a mixed gas of hydrogen and nitrogen; and forming a titanium nitride on the titanium film. Accordingly, the method can decrease a contact resistance of the tungsten interconnection in a contact hole.

Abstract: In a method of forming a self-aligned contact, gates are formed on a semiconductor substrate in a striped pattern. Bit lines are formed in a striped pattern that extends cross-wise to the gates. The bit lines are isolated from one another by a first interlayer insulation layer. Next, a second interlayer insulation layer is formed between the bit lines, and a photoresist film pattern is formed on the second interlayer insulation layer. The photoresist film pattern is used for forming contact holes extending between the gates down to conductive pads. The contact holes are filled to form conductive plugs that contact the conductive pads. The photoresist film pattern is formed as a series of stripes which extend parallel to the gates.

Abstract: A semiconductor chip molding apparatus includes an upper platen including an upper mold, a lower platen including a lower mold having a molding block configured to receive a lead frame, a controller, and an electrical detector for forming an electrical circuit between the controller and the lead frame when the lead frame is oriented improperly on the lower mold. A low-level test voltage is imparted to at least the lower mold. As a result, an electrical signal will flow from the detecting block when the lead frame rests on the detecting block. When such a signal is detected, therefore, the lead frame is determined as having been improperly set on the molding block. The signal generated is detected by a controller and used thereby to interrupt the operation of the molding apparatus.

Abstract: A multi-layered dielectric layer wherein the adhesion characteristic of an insulating layer including a Si—CH3 bond is improved, and a method of forming the same are provided. The multi-layered dielectric layer is formed on conductive patterns and includes a first insulating layer formed of a layer having a low dielectric constant including the Si—CH3 bond. In order to improve the adhesion characteristic of the first insulating layer, an adhesion surface is formed on the surface of the first insulating layer by treating the first insulating layer with plasma. In an alternative, the adhesion characteristics of the first insulating layer is improved by forming a buffer layer on the first insulating layer so that dipole—dipole interaction occurs between the first insulating layer and the buffer layer.

Abstract: First pad electrodes for connection to leads and second pad electrodes for an internal interface, are provided over a main surface of a first LSI chip. Third pad electrodes of a second LSI chip and the second pad electrodes of the first LSI chip are respectively electrically connected to one another by wires. Circuits required as for a system LSI, which are not included in the LSI chip, are placed over the LSI chip, to implement a desired function used as for the system LSI by the two LSI chips. The system LSI is easily implemented by a semiconductor device wherein a plurality of LSI chips are sealed with a resin.

Abstract: A semiconductor device includes, a die pad having a top surface and a bottom surface, a first semiconductor chip having a top surface on which electrodes are formed and a bottom surface, and a second semiconductor chip having a top surface on which electrodes are formed, and a bottom surface, the second semiconductor chip being smaller than the first semiconductor chip, wherein the first chip top surface is fixed on the die pad bottom surface, the second chip bottom surface is fixed on the die pad top surface.

Abstract: A method of manufacturing a semiconductor device including forming an insulator layer on an integrated circuit, forming a barrier layer having a first titanium film and a titanium nitride film on the insulator layer, heat-treating the barrier layer to release nitrogen gas from the titanium nitride film, forming a second titanium film on the barrier layer, and forming an aluminum film used as a wired metal on the second titanium film.

Abstract: A gas supplying apparatus of a system for fabricating semiconductor devices is tested for clogs. The gas supplying apparatus includes a carrier gas supplying device for supplying at least one carrier gas, and a plurality of reactive gas supplying devices connected in parallel to the carrier gas supplying device. The reactive gas supplying devices gasify the reactive gas carried by the carrier gas. A wafer, on which a desired layer is to be formed, is situated in a process chamber into which the reactive gas is supplied from the reactive gas supplying devices. The gas supplying apparatus also includes pressure detecing devices for detecting the pressure of the carrier gas near each of the reactive gas supplying devices. The carrier gas is supplied under a predetermined pressure to the reactive gas supplying devices. The reactive gas supplying device to be tested for clogs is rendered operational while the other reactive gas supplying devices are shut down.

Abstract: A method of manufacturing a waveguide optical semiconductor device provides a semiconductor substrate including a lower clad layer, a core layer, an upper clad layer and a contact layer formed on the substrate in order. The contact layer and a part of the upper clad layer are removed by dry etching between a pair of parallel line patterns and at an independent rectangular pattern located near the line patterns. Then, the remaining upper clad layer is removed by wet etching so as to expose the core layer within the line patterns and the independent rectangular pattern. An insulating material is coated on the exposed core layer. The insulating material formed on the contact layer is removed within a region located between the pair of line patterns so that a part of the contact layer is exposed. An electrode layer is formed on the exposed contact layer. Finally, a bonding pad layer is formed over the independent rectangular pattern and a part of the electrode layer.

Abstract: A semiconductor device includes a semiconductor chip having a bump electrode over its main surface. The bump electrode has at least one protrusion on the top surface thereof. A lead is electrically connected to the top surface of the bump electrode, and is positioned adjacent to the protrusion.

Abstract: An evaluating pattern is comprised of a conductive pattern which has a rectangular configuration, an insulating layer which is formed on the conductive pattern, and a conductive material filled into contact holes which is formed in the insulating layer on the middle of the conductive pattern.

Abstract: A drive circuit includes an input node for receiving data and an output node. The drive circuit also includes a first MOS transistor of a first conductivity type and a second MOS transistor of the first conductivity type. The first MOS transistor has a source, a drain connected to the output node, and a gate connected to the input node. The second MOS transistor has a source, a drain connected to the source of the first MOS transistor, and a gate supplied with a predetermined potential level. The drive circuit also includes a resistance connected between the source of the second MOS transistor and a source node supplied with a source potential level.

Abstract: A method for correcting line width variation occurring during a development process in fabricating a photomask and a recording medium in which the exposure method is recorded is provided, wherein pattern line width variation occurring in a development process with respect to a desirable pattern is estimated, and a corrective exposure is performed using a dose or bias of an electron beam corresponding to the estimated pattern line width variation. Accordingly, pattern line width variation occurring during a development process can be reduced.

Abstract: The sealing resin of a semiconductor device is prevented from being peeled off from the substrate of the semiconductor device. A semiconductor device according to the present invention has a semiconductor substrate containing a central portion having a first thickness and a peripheral portion having a second thickness that is smaller than the first thickness, an electrode pad formed on the semiconductor substrate, a sealing resin for sealing the semiconductor substrate, a protruded electrode formed on the sealing resin, and a wire which electrically connects the electrode pad to the protruded electrode.

Abstract: In a method of manufacturing a semiconductor device, a semiconductor substrate including an insulating layer is provided. A groove is formed on the insulating layer. An additive-containing barrier layer is formed on the insulating layer. A metal seed layer and a metal layer are formed on the barrier layer. Then, the metal layer is subjected to a first heat treatment at a first temperature that is capable of promoting grain growth of the metal seed layer and the metal layer. The barrier layer, the metal seed layer and the metal layer are partially removed so that a conductive layer including the metal seed layer and the metal layer is formed in the groove. Finally, the conductive layer is subjected to a second heat treatment at a second temperature that is higher than the first temperature and allows an additive element in the barrier layer to diffuse into the metal layer.