Abstract: An electron beam lithography method includes extending the widths of a plurality of stripes which divide a region where an electron beam exposure is to be performed, so that the boundaries of the stripes overlap adjacent stripes at each boundary, and sequentially exposing each of the stripes to an electron beam.

Abstract: This invention relates to a method of depositing a tantalum film in which ?-Ta dominates and to methods of electroplating copper using such films. The films have a thickness of less than 300 nm and are formed by depositing a seed layer of an organic containing low dielectric constant insulating layer and sputtering tantalum onto the seed layer at a temperature below 250° C.

Abstract: A semiconductor apparatus includes a semiconductor integrated circuit including a conductive pattern; an insulating layer which is formed on the semiconductor integrated circuit to forms a plurality of base members having uneven heights; an opening which is formed through the insulating layer to expose a part of the conductive pattern; and a conductive layer which is formed on the insulating layer and the opening, the conductive layer is extending from the exposed portion of the conductive pattern to the top surface of the highest base member. An electrode is composed of the insulating layer, the opening and the conductive layer.

Abstract: To reduce a current loss through a channel and improve electron mobility, a first semiconductor layer and a second semiconductor layer (sequentially formed on a semiconductor substrate) have different lattice properties. The first semiconductor layer and the second semiconductor layer may be etched to form a first semiconductor pattern. A third semiconductor layer having a lattice property substantially identical to that of the first semiconductor layer may be formed over the first semiconductor pattern. The third semiconductor layer may then be etched to form a second semiconductor pattern. A gate may be formed on the second semiconductor pattern. The contact surface between the second semiconductor pattern and the gate pattern may consequently increased to reduce a current loss. Further, the lattice properties may be changed to improve electron mobility of the semiconductor layers.

Abstract: A method of forming a capacitor for a semiconductor device is disclosed. According to the method, a silicon germanium layer and an oxide layer are used as mold layers for forming a storage electrode. The oxide layer and the silicon germanium layer are anisotropically etched to form an opening and then the silicon germanium layer is further isotropically etched to form a recessed portion of the opening, such that the recessed portion of the opening formed in the silicon germanium layer is wider than at least some portion of the opening through the oxide layer. Thus, the mold layers are used to form a storage electrode having a lower portion which is wider than an upper portion thereof.

Abstract: An analog circuit includes a pair of peak-hold circuits that generate peak signals indicating the peak values of a differential pair of input signals, a first differencing circuit such as a transconductance amplifier that takes the difference between the input signal values, a second differencing circuit such as a transconductance amplifier that takes the difference between the two peak signal values, and a combining circuit such as a resistor circuit that additively combines the outputs of the differencing circuits in such a way as to compensate for direct-current offset in the input signals. Advantages of this circuit structure include reduced power consumption and simplified implementation in an integrated circuit. Low pass filters, capacitor discharging circuits, and unbalanced circuit elements can be used to obtain further advantages.

Abstract: A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which comprises a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the first conductive layer and the first barrier layer. Accordingly, the semiconductor device can avoid a problem so that the Cu of the first main interconnection transfers from a portion connected to the second interconnection due to cause electromigration, the connected portion becomes a void, and the first interconnection is disconnected to the second interconnection.

Abstract: A semiconductor device having a delay-locked loop includes: a variable delayer that delays a clock signal for a predetermined period of time to generate an internal clock signal; a normal pass that outputs data read from a memory cell outside the semiconductor device in response to the internal clock signal; a replica pass that has a substantial identical time delay to the normal pass and delays the internal clock signal to generate an output signal; and a phase detector that compares a phase of the clock signal with a phase of a predetermined feedback clock signal to control a time delay in the variable delayer. Here, the internal clock signal is output, instead of the output signal from the replica pass, as the predetermined feedback clock signal in a predetermined test mode.

Abstract: Long file names found in an application program are contained in array. Then, short file name corresponding to each long file name is made; by combining the number of array element containing the corresponding long file name, with prescribed letter row. On the other hand, in the occasion of comparing newly found long file name with long file names already contained in array, only a specific byte of array element in array is compared with a specific data. Thus, efficient array searching is processed.

Abstract: A divider circuit including a plurality of latch circuits which are connected in series such that each of the latch circuits is responsive to a control signal to latch data which is output from a preceding latch circuit in the series, and a logic circuit which receives the data output from the plurality of latch circuits and which outputs a logic operation result to a first latch circuit in the series of the plurality of latch circuits.

Abstract: A system and method of wavefront sensing with a Shack-Hartmann wavefront sensor precisely locates focal spots on a detector array, and determines the location of the lenslet array with respect to the detector array.

Abstract: CVD is performed without damaging a micro-fabricated semiconductor element. An organic material gas containing amine is used as deposition material gas. The material gas is introduced into a vacuum chamber and ultraviolet light radiated from each of lamps is applied onto an object to be processed that is placed in the chamber, thereby causing chemical vapor deposition to be carried out, whereby a film is grown at a temperature such that no damage is given to a semiconductor element or the like of the object.

Abstract: A semiconductor manufacturing apparatus includes a wafer support having a grinding base on which a wafer is disposed, and a grinding assembly disposed above the grinding base. The grinding assembly includes a grinding plate having grinding projections at the bottom thereof and at least two fixing pins protruding at a the top thereof, and a grinding mount to which the grinding plate to which the grinding plate can be initially coupled and then secured to quickly. The grinding mount has first fixing grooves in a bottom surface thereof and in which the respective fixing pins are inserted and held. A vacuum system and/or mechanical fasteners are used to then secure the grinding plate to the grinding mount.

Abstract: A semiconductor wafer has different impurity concentrations in respective regions and gate patterns have different lengths in the respective regions. The semiconductor wafer has different impurity concentrations in a central region, an intermediate region, and an outer region. The gate patterns have different lengths in the central region, the intermediate region, and the outer region. Accordingly, the semiconductor wafer may have a substantially uniform threshold voltage throughout the semiconductor wafer.

Abstract: A method of manufacturing a waveguide type optical element wherein Zn is selectively diffused on a light absorption layer using an undoped InP layer. Since an impurity diffusion area is made on the light absorption layer under a ridge part, a depletion layer becomes thin in a thickness direction and an electric field can strongly be applied. Thereby, an extinction ratio characteristic of a device can be improved.

Abstract: A duty cycle correction circuit and a delay locked loop (DLL) including the duty cycle correction circuit, are capable of controlling their operation in order to correctly analyze the cause of generation of a duty cycle error when the duty cycle error is generated in the DLL. The duty cycle correction circuit selectively outputs to a DLL core duty cycle offset information for controlling a duty cycle of an internal clock signal synchronized to an external clock signal under the control of a switching control signal. The DLL corrects the duty cycle of a reference clock signal according to the duty cycle offset information, thereby outputting a reference clock signal having a 50% duty cycle.

Abstract: A method of manufacturing a floating gate provides an enhancement for the efficiencies of electron charge and injection. First, a conductive pattern, constituting the floating gate is formed on a substrate. A first insulation layer is formed on a sidewall of the conductive pattern, and then a second insulation layer is formed at an upper portion of the conductive pattern in ways that increase the sharpness of an edge portion where the sidewall and upper portions of the conductive pattern meet. Therefore, electron transference from the floating ate to a control gate is facilitated.

Abstract: A ramp signal generation circuit is disclosed. The ramp signal generation circuit comprises a ramp signal generator, a buffer, a comparator, and a switching circuit. The switching circuit provides current to an output of the ramp signal generation circuit in response to a control signal output by the comparator. When a high slew rate is required, the output of the ramp signal generation circuit is driven by the current provided by the switching circuit. Otherwise, the output of the ramp signal generation circuit is driven by an output of the buffer.

Abstract: A data transmission circuit includes a control signal generation circuit, a write state machine, a conversion circuit, a read state machine, and a selection circuit. The control signal generation circuit receives a strobe signal and a clock signal in response to an enable signal, generates a write control signal that is activated in response to a rising edge of the strobe signal, and generates a read control signal that is activated in response to a first rising or falling edge of the clock signal after the write control signal is activated. The write state machine is activated in response to the write control signal, changes its internal state in synchronization with the strobe signal, and sequentially outputs input control signals in response to the changed internal state. The conversion circuit converts serial data to parallel data in response to the input control signal sequentially output from the write state machine and latches the parallel data.

Abstract: A method of manufacturing a chromeless phase shift mask includes forming a photoresist film pattern on a wafer using a basic form of the chromeless phase shift mask and measuring a specification of the photoresist film pattern. The basic form of the chromeless phase shift mask is isotropically etched to modify the phase shifter of the mask unless the photoresist film pattern specification is within a specified range. Accordingly, an application-specific chromeless phase shift mask can be produced for use in any exposure apparatus and under any exposure condition.