Abstract: A local timer includes a dividing counter which counts a first clock and outputs a reference counting signal divided from the first clock; a timing synchronizing timer which counts a timing synchronizing timer value in synchronization with a reference timer responsive to the reference counting signal; a first buffer which stores a counted value of the dividing counter in synchronization with a second clock, when operation is by the first clock; a second buffer which stores the timing synchronizing timer value in synchronization with the second clock, when operation is by the first clock; a first adder which adds a first or second offset value to the stored value in the first buffer in synchronization with the second clock, when the first clock is suspended; and a second adder which adds a set value to the timing synchronizing timer value responsive to a carry from the first adder.

Abstract: A Flash memory that stores data, code, and parameters and performs parallel operations employs uniform-size blocks in array planes. A redundancy system for the Flash memory uses a CAM and a RAM for address comparison and substitution when replacing addresses corresponding to defective memory elements. The uniform block size allows block replacement where spare blocks in the array planes replace defective blocks. To reduce access delays from signal propagation through the CAM and RAM, part of the input address such as the row address goes directly to decoders while another part of the input address such as the block address goes to the CAM array for comparison.

Abstract: An output driver may reduce coupling noise. The output driver may include a first transistor, a second transistor, and/or a noise-eliminating portion. The first transistor may have a first terminal connected to a first voltage, a second terminal connected to a first node, and a gate to which data is applied. The second transistor may have a first terminal connected to the first node and a second terminal connected to an output node. The noise-eliminating portion may be connected between the gate of the first transistor and a gate of the second transistor. The noise-eliminating portion may be a capacitor. The capacitor may substantially eliminate coupling noise introduced at the gate of the second transistor, due to coupling capacitance between the gate of the second transistor and the output node and coupling capacitance between the gate of the second transistor and the first node, by using the data applied to the gate of the first transistor.

Abstract: A controlled release preparation of insulin and its method are provided. The controlled release preparation of insulin contains microparticles obtained by microencapsulation of uniform microcystals of insulin using biodegradable polymeric materials. Since the denaturation of insulin that may occur during microencapsulation is reduced, the stability of the preparation can be increased. Also, the ratio of insulin to a polymer carrier is increased, which is suitable for pulmonary delivery. Further, the controlled release preparation of insulin can continuously exhibit pharmaceutical efficacy in vivo in a stable manner for an extended period of time.

Abstract: A hard macro cell which prevents signal delay and quality deterioration of signal waveforms without requiring excessively long wires, and a semiconductor integrated circuit using the hard macro cell. The semiconductor integrated circuit includes the hard macro cell and other hard macro cells, which are functional blocks for performing predetermined functions. The hard macro cell is provided with input/output terminals for connecting the hard macro cell with the other hard macro cells, a repeater for overcoming signal delay and for improving the quality of signal waveforms, and an input terminal and an output terminal for connecting global wires which connect the other hard macro cells to the repeater. Signals outputted from an output terminal of one of the other hard macro cells are inputted to an input terminal of another of the other hard macro cells via the global wires and the repeater.

Abstract: A chromeless photomask includes a main pattern portion and a complementary pattern portion formed in the surface of the transparent mask substrate adjacent to an outer peripheral edge of the main pattern portion. The main and complementary pattern portions are each formed by recessing a surface of a transparent mask substrate to produce respective protrusions and recesses that induce a phase difference of 180 degrees in light rays passing therethrough. The complementary pattern portion is designed to produce interference that prevents distortion in the photoresist pattern formed at a region by and corresponding to the edge of the main pattern portion of the photomask. Accordingly, the present invention provides for a relatively large secondary mask alignment margin.

Abstract: The photosensitive polymer includes a first monomer which is norbornene ester having C1 to C12 aliphatic alcohol as a substituent, and a second monomer which is maleic anhydride. A chemically amplified photoresist composition, containing the photosensitive polymer, has an improved etching resistance and adhesion to underlying layer materials, and exhibits wettability to developing solutions.

Abstract: A semiconductor integrated circuit device has a fuse device that can be electrically disconnected without a breakage caused by using a laser beam or current. The semiconductor integrated circuit device employs, as the fuse device for storing status information, a MOSFET of a single polysilicon EEPROM-type cell manufactured through a process of fabricating a volatile semiconductor memory cell array.

Abstract: The present optically modulated scatterer comprises a substrate, an antenna positioned on the substrate, an optical switch connected to the antenna, and an optical waveguide connected to the optical switch. The antenna includes a first conductive line and a second conductive line, the optical switch electrically connects the first conductive line and the second conductive line, and the optical waveguide can transmit an optical modulating signal to the optical switch. In addition, the antenna can be a loop-shaped antenna with two free ends, and the optical switch electrically connects the two free ends. The optically modulated scatter array of the present invention comprises a first substrate and a plurality of optically modulated scatterers positioned on the surface of the first substrate in a one-dimensional or a two-dimensional array manner.

Abstract: A method of forming a conductive pattern of a semiconductor device includes forming a conductive layer is on a substrate, forming a polishing protection layer on the substrate including over the conductive layer, and forming a step compensation layer on the polishing protection layer to reduce the step presented by the layer that is the polishing protection layer. The conductive layer is the exposed by removing select portions of the step compensation layer and the polishing protection layer. The conductive pattern is ultimately formed on the substrate by etching the exposed conductive layer. By planarization the intermediate structure several times once the step compensation layer is formed, a highly uniform conductive layer is sure to be formed.

Abstract: The present invention relates to a method and apparatus for automatically measuring the concentration of total organic carbon (TOC) in chemicals and ultra-pure water that are used in a wet etch process. The apparatus includes a sampling line extending from a processing bath, and a pump, for extracting a fluid sample from the processing bath, a buffer for filtering foreign material or air bubbles from the fluid, and an analyzer for analyzing the concentration of TOC in the fluid.

Abstract: A sense amplifier includes: a bit line and a complementary bit line; a data input/output line and a complementary data input/output line; first and second transistors which are connected in series between the data input/output line and the bit line; and third and fourth transistors which are connected in series between the complementary data input/output line and the complementary bit line, where the gate of the first transistor is connected to the complementary data input/output line, the gate of the third transistor is connected to the data input/output line, and a write column select line enable signal is input to the gates of the second and fourth transistors. Since the sense amplifier can write data before data of adjacent bit line pairs are amplified in a semiconductor memory device, the write timing can be reduced.

Abstract: A projected iterative descent method is used to resolve LCPs related to rigid body dynamics, such that animation of the rigid body dynamics on a display system occur in real-time.

Abstract: A memory system using a simultaneous bi-directional input/output (SBD I/O) circuit on an address bus line. The memory system includes a first address I/O circuit and a second address I/O circuit, which are connected by the address bus line. The first address I/O circuit may be included in a controller, transmits an address signal to the address bus line, and receives an acknowledgement signal from the address bus line. The second address I/O circuit may be included in a memory device (such as dynamic random access memory (DRAM)), transmits the acknowledgement signal to the address bus line, and receives the address signal from the address bus line. The memory system may also include an error correction circuit unit which generates the acknowledgement signal indicating if an error is present in the address signal received by the second address I/O circuit.

Abstract: A mesh-shaped gate electrode is located over a surface of a substrate. The mesh-shaped gate electrode includes a plurality of first elongate wirings extending parallel to one another, and a plurality of second elongate wirings extending parallel to one another. The first elongate wirings intersect the second elongate wirings to define an array of gate intersection regions over the surface of the substrate and to further define an array of source/drain regions of the substrate. To reduce gate capacitance, at least one oxide region may be located in the substrate below the mesh-shaped gate electrode. For example, an array of oxide regions may be respectively located below the array of gate intersection regions.

Abstract: A non-volatile, multi-bit-per-cell, Flash memory uses a storage process and/or architecture that is not sector-based. A data block can be stored without unused storage cells remaining in the last sector that stores part of the data block. For an operation erasing one or more data blocks, data blocks to be saved are read from an array and stored temporarily in a storage device. The entire array is then erased, after which the saved data blocks are rewritten in the memory with the amount of storage originally allocated to the erased data now being available for new data. This data arrangement does not subject any memory cells to a large accumulated cell disturbance because all data is read from the array and freshly re-written back into the array every time a record operation occurs. Additionally, the separate sectors in the memory device do not have different endurance histories that must be accounted for to extend the life of the memory.

Abstract: A simultaneous bi-directional (SBD) transceiver includes a first, second, third and fourth differential amplifiers, where the third differential amplifier responds to signals input through data transmission channels, and the fourth differential amplifier responds to output signals derived from the first differential amplifier. The first and second differential amplifiers are fully differential amplifiers. A size of a constant current source associated with the second differential amplifier is n (n>1) times that of a constant current source associated with the first differential amplifier. A size of a constant current source associated with the third differential amplifier is m (m>1) times that of a constant current source associated with the fourth differential amplifier.

Abstract: A semiconductor memory device with a data output circuit that flexibly sets an initial value of a driver strength using fuses.

Abstract: A multi-bit-per-cell non-volatile memory performs periodic refresh operations. The refresh operations can be timed according to a maximum tolerable drift for threshold voltages representing the data and an expected rate of drift of the threshold voltage. The refresh operation can move data to different physical storage locations and extend the life of a non-volatile memory by avoiding repetitive erasing and writing of the same data value in the same memory cell. A memory mapping circuit in the memory adjusts for different storage configuration that the refresh operations create. In a particular embodiment, a refresh operation swaps the physical locations of two data blocks, and alternates between two mappings of physical addresses to logical addresses.

Abstract: A method for manufacturing a liquid crystal display which reduces the number of photolithography processes is provided.