Patents Represented by Attorney Volentine & Whitt, P.L.L.C.
  • Patent number: 8044484
    Abstract: The present invention provides an ultraviolet detecting device which comprises a silicon semiconductor layer having a thickness ranging from greater than or equal to 3 nm to less than or equal to 36 nm, which is formed over an insulating layer, lateral PN-junction type first and second photodiodes formed in the silicon semiconductor layer, an interlayer insulating film formed over the silicon semiconductor layer, a first filter layer made of silicon nitride, which is formed over the interlayer insulating film provided over the first photodiode and causes light lying in a wavelength range of an UV-B wave or higher to pass therethrough, and a second filter layer made of silicon nitride, which is formed over the interlayer insulating film provided over the second photodiode and allows light lying in a wavelength range of an UV-A wave or higher to pass therethrough.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: October 25, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Noriyuki Miura, Tadashi Chiba
  • Patent number: 7985638
    Abstract: A semiconductor device manufacturing method which sequentially forms a gate oxide film and gate electrode material over a semiconductor layer of an SOI substrate and patterns the material into gate electrodes. The method further comprises the steps of forming sidewalls made of an insulator to cover side surfaces of the gate electrode; ion-implanting into the semiconductor layer on both sides of the gate electrode to form drain/source regions; partially etching the sidewalls to expose upper parts of the side surfaces of the gate electrode; depositing a metal film to cover the tops of the drain/source regions and of the gate electrode and the exposed upper parts of the side surfaces of the gate electrode; and performing heat treatment on the SOI substrate to form silicide layers respectively in the surfaces of the gate electrode and of the drain/source regions.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: July 26, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Masao Okihara
  • Patent number: 7957950
    Abstract: A hard/soft cooperative verifying simulator is based on a SystemC simulator, and provides the capability of reducing overhead of context switching control thereby to shorten processing time. Time keepers for controlling simulation times of a plurality of threads are provided corresponding to the threads generated as simulation models for hardware and software. Each of the time keepers has a variable which holds a simulation time for each thread, a variable which holds a summation time, and a break request queue which stores a break time and its corresponding break method therein. The time keeper manages both variables and the queue in response to six types of method invocations from the thread, and invokes a wait function of the SystemC simulator when necessary. It is thus possible to reduce the number of times that a wait function invocation is performed, and shorten the entire processing time.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: June 7, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Noriyoshi Ito
  • Patent number: 7956784
    Abstract: A DA converter includes an IV conversion amplifier with output voltage having good linearity, to thus improve total harmonic distortion (THD) characteristics. In the DA converter, a first current path in which current flows due to differential switches being in the ON state in a differential switch section, and a second current path in which current flows due to differential switches being in the OFF state in the differential switch section are connected to the output side of the IV conversion amplifier. A first current flows in the first current path and a second current flows in the second current path. A current equal to the first current plus the second current that is of fixed current amount is drawn by an amplifier stage of the IV conversion amplifier.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: June 7, 2011
    Assignee: Oki Semiconductor Co., Ltd
    Inventors: Kouji Morita, Naoaki Sugimura, Masaru Sekiguchi
  • Patent number: 7955933
    Abstract: A method of manufacturing a nonvolatile semiconductor memory device includes the steps of preparing a wafer having multiple memory cells, each memory cell having a gate electrode formed on a semiconductor substrate, charge storage units formed on both sides of the gate electrode, lightly doped regions formed beneath the charge storage units, respectively, in the upper part of the semiconductor substrate, and highly doped regions formed in a pair of regions sandwiching a region underneath the gate electrode and the lightly doped regions in between; erasing data stored in the charge storage units electrically; and treating the wafer at a high temperature for a predetermined period of time.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: June 7, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Narihisa Fujii, Takashi Ono
  • Patent number: 7956430
    Abstract: An accelerator sensor includes a semiconductor substrate having a main front surface and a main rear surface, a first groove portion being formed along a front surface pattern, in the main front surface, a second groove portion being formed along a rear surface pattern, in the main rear surface, a through-hole being formed because of connection between at least parts of the first groove portion and the second groove portion and at least one groove width variation portion being formed in at least one of inner walls of the first groove portion. An offset of the rear surface pattern to the front surface pattern can be inspected easily by existence of the groove width variation portion.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: June 7, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yoshihide Tasaki
  • Patent number: 7952118
    Abstract: A semiconductor includes a channel region in a semiconductor substrate, a gate dielectric film on the channel region, and a gate on the gate dielectric film. The gate includes a doped metal nitride film, formed from a nitride of a first metal and doped with a second metal which is different from the first metal, and a conductive polysilicon layer formed on the doped metal nitride film. The gate may further include a metal containing capping layer interposed between the doped metal nitride film and the conductive polysilicon layer.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: May 31, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung-suk Jung, Jong-ho Lee, Sung-kee Han, Ha-jin Lim
  • Patent number: 7948300
    Abstract: A negative supply voltage generating circuit includes a pulse generating circuit and a charge pump. The pulse generating circuit generates a first pulse signal and a second pulse signal in response to a clock signal. The first and second pulse signals have pulse widths different from each other. The charge pump generates a negative supply voltage by performing a charge pumping operation in response to the first and second pulse signals, and has a time interval between a switch-on time duration for charging a flying capacitor and a switch-on time duration for transmitting charges to an output capacitor.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: May 24, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ji-Yeoul Ryoo
  • Patent number: 7948794
    Abstract: A nonvolatile memory device includes multiple memory blocks divided into multiple memory block groups. Each memory block group includes at least two memory blocks of the multiple memory blocks. The nonvolatile memory device also includes a main word line common to the memory blocks, and multiple sub-word lines corresponding to the memory blocks. Sub-word lines of the multiple sub-word lines located within the same memory block group are electrically connected to each other, and sub-word lines of the multiple sub-word lines located in different memory block are electrically isolated from each other.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: May 24, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Byung-Gil Choi
  • Patent number: 7948278
    Abstract: The present invention provides a load capacity driving circuit that is inexpensive and has a high driving capability. When an input signal changes to low potential, gate voltage of an output stage of an amplifying circuit increases, an NMOS transistor MNO turns on, and an NMOS transistor MN8 increases potential of a node NGAT. Due thereto, an NMOS transistor MNO2 also turns on, and a load capacity is discharged via the NMOS transistor MNO and the NMOS transistor MNO2. Further, when the input signal changes to high potential, gate voltage of the output stage of the amplifying circuit decreases, a PMOS transistor MPO turns on, and a PMOS transistor MP8 decreases potential of a node PGAT. Due thereto, a PMOS transistor MPO2 also turns on, and the load capacity is charged from a constant voltage source via the PMOS transistor MPO and the PMOS transistor MPO2.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: May 24, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Hideaki Hasegawa, Koji Higuchi, Atsushi Hirama, Koji Yamazaki
  • Patent number: 7947563
    Abstract: A chip forming position specifying method for applying chip IDs indicative of positions on a wafer where semiconductor chips are formed, and thereby specifying their positions. In the chip forming position specifying method, different marks are formed for every chip in a transfer mask (hereinafter called “mark forming mask”) used to form a wiring layer, in addition to normal functional wirings. The positions of the chips on the wafer are respectively specified according to combinations of the marks of a plurality of the mark forming masks, which have been transferred onto the wafer.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: May 24, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Shigenari Aoki
  • Patent number: 7944058
    Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode, A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: May 17, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Masamichi Ishihara
  • Patent number: 7944747
    Abstract: Provided is a method for programming a flash memory device. The method includes receiving writing data, detecting leakage bit lines of the flash memory device, and updating the received writing data in order for data corresponding to the leakage bit lines to be modified as program-inhibit data. A programming operation is performed on the flash memory device after updating the writing data.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: May 17, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hyuk Chae, Young-Ho Lim
  • Patent number: 7945062
    Abstract: The invention relates to a microelectromechanical microphone packaging system. The microelectromechanical microphone packaging system comprises a substrate, a chip, a microelectromechanical microphone, a conductive glue, a non-conductive glue and a cover. The substrate has a first surface. The chip is mounted on the first surface of the substrate. The microelectromechanical microphone is mounted on the first surface of the substrate, and electrically connected to the chip. The chip is enclosed by the non-conductive glue. The non-conductive glue is enclosed by the conductive glue. The cover is mounted on the first surface of the substrate to form a containing space, and has an acoustic aperture. The microelectromechanical microphone packaging system utilizes the conductive glue enclosing the chip and the non-conductive glue to shield interference from outside noise and obtain a shielding effect. In addition, the cover does not need to be made of metal material.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: May 17, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei-Chung Wang, Sung-Mao Wu, Hsueh-An Yang, Kuo-Pin Yang, Chian-Chi Lin
  • Patent number: 7939379
    Abstract: A hybrid carrier and a method for making the same, wherein the hybrid carrier has a plurality of interconnection leads, so that a wire bondable semiconductor device or a flip chip die apparatus can be placed on the hybrid carrier, and is electrically connected to die paddle and bond fingers. Also, it is easy to dispose a semiconductor device on the hybrid carrier and easy to electrically bond the hybrid carrier and the semiconductor device. Therefore, the hybrid carrier and the method for making the same can be applied to an area array metal CSP easily, and the method is simple, so the production cost can be reduced.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: May 10, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Sung-Ho Youn, Hyeong-No Kim
  • Patent number: 7936232
    Abstract: A substrate for a semiconductor package includes a dielectric substrate, a circuit pattern formed on a first surface of the dielectric substrate, and an electromagnetic band gap (EGB) pattern. The EGB pattern includes multiple unit structures formed on a second surface of the dielectric substrate, where each unit structure includes a flat conductor electrically connected to the circuit pattern through a ground connection, and multiple spiral-patterned conductors electrically connected to the flat conductor. The second surface is formed on an opposite side of the dielectric substrate from the first surface. Each flat conductor is electrically connected to a flat conductor of another one of the unit structures. At least one of the spiral-patterned conductors in each one of the unit structures is electrically connected to another one of the spiral-patterned conductors.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: May 3, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-seok Song, Hee-seok Lee, So-young Lim
  • Patent number: 7932597
    Abstract: A BGA substrate which has a back surface to which a heat radiating plate is attached and an opening for accommodating a relay wiring substrate therein, which is provided in the center of its surface, is used. The relay wiring substrate to which an ASIC chip and a memory chip are flip-chip connected, is bonded to the heat radiating plate in the opening with a thermal conductive bonding material. Further, each of the back surfaces of the ASIC chip and the memory chip is connected to a metal cap for sealing the opening through a thermal conductive material interposed therebetween.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: April 26, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Makoto Terui, Yasushi Shiraishi
  • Patent number: 7927499
    Abstract: A substrate having a blind hole and a method for forming the blind hole. The method includes: (a) providing a substrate having a lower dielectric layer, a copper layer, and an upper dielectric layer; and (b) forming an upper dielectric layer through hole and a copper layer through hole by etching through the upper dielectric layer and the copper layer with laser, and forming a cavity on the lower dielectric layer by using the laser, in which the aperture of the cavity on the upper surface of the lower dielectric layer is larger than that of the copper layer through hole. Therefore, a blind hole space in a shape of a rivet is formed, so that after the blind hole space is electroplated with an electroplating copper layer, the bonding force between the electroplating copper layer and the copper layer is enhanced.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: April 19, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Te-Chun Wang
  • Patent number: 7928718
    Abstract: A method of calibration of a particle characterization apparatus, and a particle characterization apparatus, in which particles suspended in a liquid are passed through an orifice one by one for characterization of the particles, for instance by Coulter counting. The calibration does not require utilization of special calibration particles or liquids. A priori knowledge of the shape of a typical size distribution of a blood sample is utilized to adjust the apparatus based on an initial relatively short counting period of the sample in question. The initially determined size distribution is compared to the corresponding known typical size distribution and the apparatus is subsequently adjusted to counteract possible differences. Upon adjustment of the apparatus, the remaining part of the sample is passed through the orifice for determination of the actual particle size distribution of the remaining sample.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: April 19, 2011
    Assignee: Chempaq A/S
    Inventor: Ulrik Darling Larsen
  • Patent number: 7927951
    Abstract: A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: April 19, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Whan Kim, Kae-Dal Kwack, Sang-Su Park