Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, where each memory cell includes a transistor with a floating body region in which majority carriers are accumulated in a steady state. In write and read operations, a first data state corresponding to the steady state is written to and read from at least one selected memory cell of the memory cell array by supplying a first bipolar current through the at least one selected memory cell, and a second data state is written to and read from the at least one selected memory cell by supplying a second bipolar current which is smaller than the first bipolar current through the at least one selected memory cell. In a refresh operation, memory cells of the memory cell array storing the second data state are refreshed.

Abstract: A magneto-sensitive integrated circuit which amplifies a magneto-sensitive output voltage of a Hall element by an amplifier to generate an amplified voltage, converts an output voltage of the amplifier into a digital signal by an A/D converter; and generates a reference voltage of magnitude corresponding to an indicated value. The amplifier includes a voltage superposition element which superposes a DC voltage corresponding to the reference voltage on the amplified voltage to generate the output voltage of the amplifier.

Abstract: A semiconductor wafer has a substrate, and a plurality of active areas formed on the substrate. Integrated circuits are formed in the active areas. The semiconductor wafer also has dicing areas formed between the adjacent active areas. A seal ring is formed along the edge (periphery) of each active area. The semiconductor wafer also has interconnects formed closely to the inside of the seal ring. A protective layer covers the active areas. A protective film is formed on the protective layer at the locations of the active areas. The semiconductor wafer also has another interconnects formed on the protective film for electrical connection to the integrated circuits. Preferably, when the aspect ratio of a groove formed in the protective layer between the seal ring and the interconnect is 0.5 or more, this groove is covered with the protective film.

Abstract: An active region is provided which includes a plurality of active region columns extending in a first direction and a plurality of active region rows extending in a second direction substantially orthogonal to the first direction and having concave portions. Floating electrodes and control electrodes are provided on the active region columns. An interlayer insulating film formed as a layer below an upper wiring is provided on the active region and the control electrodes. Conductive sections that electrically connect the upper wiring and the active region are respectively provided on the concave portions on the active region rows.

Abstract: A nonvolatile memory device includes a memory cell array having multiple memory cells arranged at intersections of word lines and bit lines, a first page region configured with at least two adjacent memory cells coupled to a word line, and a second page region configured with at least two adjacent memory cells coupled to the word line. The nonvolatile memory devices also includes a first common source line connecting with the memory cells of the first page region, and a second common source line connecting with the memory cells of the second page region. The first and second common source lines are controlled independently.

Abstract: An instruction code compression method and an instruction fetch circuit which are capable of reducing both the number of fetches and program codes. A reuse flag is provided in an upper bit group including operational codes, and a lower bit group including operands and having the same number of bits as the upper bit group. When 2N+1 (N is an integer of 1 or more) instruction codes having the same upper bit group continues in a series of instruction codes, respective reuse flags of the lower bit group of a 2n-th (n is an integer of 1 or more and N or less) instruction code and a (2n+1)-th instruction code in the series of instruction codes are set to “1”, and the lower bit groups of the 2n-th and (2n+1)-th instruction codes are integreted into one compressed instruction code.

Abstract: A substrate structure having non-solder mask design (N-SMD) ball pads. The substrate structure includes a substrate and a solder mask. The substrate has a first surface, a trace layer and at least one ball pad. The ball pad and the trace layer are disposed on the first surface. The trace layer has a plurality of traces, and at least one trace electrically connects to the ball pad. The solder mask has at least one opening corresponding to the ball pad. The size of the opening is larger than that of the ball pad. The solder mask covers the trace connecting to the ball pad. The problem of non-alignment of the solder ball can thus be solved, and the hole in the solder ball can be prevented when the substrate structure is welded with a PCB so that the reliability of solder ball welding can be improved.

Abstract: A supporting base, including a supporting plate and holders, holds a sapphire substrate so that one substrate surface faces a hot plate and the other substrate surface faces a radiant heat absorbing plate mounted on the supporting plate. Radiant heat from the hot plate passes through the sapphire substrate and heats the radiant heat absorbing plate. The sapphire substrate is heated from both sides by air warmed by the hot plate and radiant heat absorbing plate, and therefore does not warp. When the temperature of the sapphire substrate has reached the necessary level, the supporting base delivers the sapphire substrate to the surface of the hot plate, then moves away while the sapphire substrate is held against the hot plate and a semiconductor fabrication process is carried out on the sapphire substrate.

Abstract: A data management method of a non-volatile memory device includes writing data and representing a state of the data. The state includes one of multiple possible states. A state of the multiple possible states corresponding to a final operation is determined as a valid state of the data.

Abstract: A method is provided for verifying a programming operation of a flash memory device. The flash memory device includes at least one memory string in which a string selection transistor, multiple memory cells and a ground selection transistor are connected in series, and the programming operation is performed with respect to a selected memory cell in the memory string. The method includes applying a voltage, obtained by adding a threshold voltage of the string selection transistor to a power supply voltage, to a string selection line connected to the string selection transistor; applying a ground voltage to wordlines connected to each of the memory cells and a ground selection line connected to the ground selection transistor; precharging a bitline connected to the memory string to the power supply voltage; and determining whether a programming operation of the selected memory cell is complete.

Abstract: A semiconductor device, a semiconductor element, and a substrate are provided, which allow the semiconductor element to be provided with a reduced size when combined. The semiconductor device has a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element includes a grayscale voltage generating unit for generating a plurality of grayscale voltages by dividing a reference voltage, a plurality of electrodes for the reference voltage formed in the neighborhood of the grayscale voltage generating unit; and an internal wiring for connecting the grayscale voltage generating unit and the reference voltage electrodes. The substrate includes a wiring pattern for the reference voltage for connecting the external input terminal and the reference voltage electrodes.

Abstract: An apex is extracted from a designed wiring layout. In start/end portion circular arc processing a circular arc is added to the apex-containing portion, and the layout data file is rewritten so that a portion, representing a region surrounded by circular arc and two lines, is added to the wiring line. In bend portion circular arc processing circular arcs are added to the respective apex-containing portions, and the layout data file is rewritten so that: a portion corresponding to a region surrounded by the circular arc and two lines is added to the apex-containing portion of the layout when the determined angle is less than 180 degrees; a portion corresponding to a region surrounded by the circular arc and two lines is removed from the apex-containing portion of the layout when the determined angle exceeds 180 degrees.

Abstract: An integrated antenna for WWAN, GPS, and WLAN includes a ground metal plane, a WWAN antenna, and a WLAN antenna. The WWAN antenna is connected to the ground metal plane and includes first and second radiating metal strips which induce a first resonance mode and a second resonance mode respectively. The WLAN antenna is connected to the ground metal plane and includes third and fourth radiating metal strips which induce a third resonance mode and a fourth resonance mode respectively. The integrated antenna can be used in WWAN and WLAN at the same time. The ground metal plane of the integrated antenna does not need to connect to a ground end of a wireless electronic device, and is used for grounding. Therefore, the integrated antenna can be mounted on any part of a wireless electronic device, and can have stable electrical characteristics.

Abstract: A wiring structure in a semiconductor device includes a first insulation layer formed on a substrate having first and second contact regions, and first and second pads extending through the first insulation layer and contacting the first and the second contact regions. The first and the second pads are higher than the first insulation layer. A blocking layer pattern is formed on the first insulation layer between the first and the second pads, the blocking layer pattern being higher than the first and the second pads. A second insulation layer is formed on the blocking layer pattern and the first and the second pads. A bit line structure is formed on the second insulation layer, the bit line structure electrically contacting the second pad. A third insulation layer is formed on the second insulation layer and the bit line structure. A plug extends through the second and the third insulation layers and contacts the first pad.

Abstract: The present invention relates to a circuit substrate comprising an upper surface, a first layout area, a second layout area, and a third layout area. The first layout area is on the upper surface, and has a plurality of first electrical contacts. The second layout area is on the upper surface, and has a plurality of second electrical contacts. The third layout area is on the upper surface, and has a plurality of third electrical contacts. The second and the third electrical contacts that have the same electrical property are electrically connected to each other. Thus, the circuit substrate can be applied to memory chips with different size.

Abstract: A semiconductor memory cell device includes a first multiplexer selecting a sub-block including a memory cell storing data to be read out in a row, a drain selector selecting a first column line connected to one terminal of the memory cell to be read, a precharge selector selecting a second column line connected to the other terminal of the memory cells adjacent to the one terminal of the memory cell storing the data to be readout, a second multiplexer selecting the sub-block including the second column line, a source selector selecting a third column line connected to the other terminal of the memory cell storing the data to be read out. The second multiplexer and precharge selector, when selecting, apply a first voltage to the second column line, and the source selector, when selecting, applies a second voltage to the third column line.

Abstract: An image device and a method of fabricating the image device include a substrate pattern formed to define an opening and to include a portion of a photodiode for receiving light. Stacked metal interconnection patterns and an interlayer dielectric layer are formed beneath the substrate pattern. A height of the opening equals a height of the substrate pattern, such that an exposed portion of a top surface of the interlayer dielectric layer provides a bottom surface of the opening. An external connection electrode is positioned on the bottom surface of the opening.

Abstract: A flash memory device includes a cell array and a decision unit. The cell array includes multiple regions corresponding to multiple input/output lines. Initialization data are repeatedly stored in each of the regions. The decision unit determines whether the stored data are valid based on values of bits of the stored data read from each region.

Abstract: Disclosed is a flash memory device which includes a memory core, a high voltage generating circuit and a reference voltage generating circuit. The high voltage generating circuit is configured to generate a high voltage to be supplied to the memory core. The reference voltage generating circuit is configured to generate at least one reference voltage to be supplied to the high voltage generating circuit. The reference voltage generating circuit includes a first reference voltage generator configured to generate a first reference voltage in response to a supply voltage, and a second reference voltage generator configured to generate a second reference voltage in response to the first reference voltage. The at least one reference voltage supplied to the high voltage generating circuit includes the second reference voltage.

Abstract: A method of forming a semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. This surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is deposited on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer having openings exposing part of the conductive pattern is formed. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The method enables the thickness of the protective layer, which may function as a package of the semiconductor device, to be reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.