Abstract: Byte-operational nonvolatile semiconductor memory devices are capable of erasing stored data one byte at a time. A byte memory cell may include a memory cell array of 1-byte memory transistors. The 1-byte memory transistors may be arranged in one direction, each including a junction region and a channel region formed in an active region. A byte memory cell may include a byte select transistor. The select transistor may be disposed in the active region and including a junction region that is directly adjacent to a junction of each of the 1-byte memory transistors. The byte select transistor may be disposed over or under the 1-byte memory transistors perpendicular to the arranged direction of the 1-byte memory transistors.

Abstract: A base substrate is first prepared, and a high dielectric amorphous film composed of a high permittivity material is formed over the base substrate. Next, an amorphous silicon film is formed over the high dielectric amorphous film with an amorphization temperature of the high permittivity material as a deposition temperature. Then, the amorphous silicon film is processed by a photolithography method and dry etching to form gate electrode forming films. Wet etching with the gate electrode forming films as masks is next performed to allow portions of the high dielectric amorphous film, which are covered with the gate electrode forming films to remain and remove exposed portions of the high dielectric amorphous film. Next, the gate electrode forming films are thermally treated to reform amorphous silicon into polysilicon so as to constitute gate electrodes.

Abstract: A digital to analog converter includes first and second capacitors, an operational amplifier and a switching circuit. The operational amplifier includes first and second input terminals and an output terminal, the second input terminal receiving a reference voltage. The switching circuit includes multiple switches which switch in response to corresponding switching signals. The switching circuit connects the second capacitor between the output terminal and the first input terminal of the operational amplifier, while respectively sending first and second voltages to first and second terminals of the first capacitor during a first period. The switching circuit also connects the first capacitor between the output terminal and the first input terminal of the operational amplifier, while respectively sending third and fourth voltages to first and second terminals of the second capacitor during a second period consecutively following the first period.

Abstract: A differential amplifier is disclosed. The differential amplifier includes a first load element coupled between a first voltage and a first node. A second load element is coupled between the first voltage and a second node. A current source is coupled between a second voltage and a third node. A first input element is coupled between the first node and the third node and receives an input signal so as to adjust a voltage level of the first node. A second input element is coupled between the second node and the third node and receives a reference voltage signal so as to adjust a voltage level of the second node. A third input element is coupled between the second node and the third node and receives the input signal so as to adjust the voltage level of the second node.

Abstract: In a step-up booster circuit, a number of pump circuits are connected in series. Pump control signals are outputted from a pump control circuit, and the pump circuits accordingly generate a required raised voltage by stepping up voltages of signals inputted to the respective pump circuits. The step-up circuit includes an activation control circuit which generates a pump activation signal in accordance with provided signals, which direct operation of the step-up circuit. The pump control circuit controls output of the pump control signals in accordance with a voltage of the pump activation signal.

Abstract: A method for fabricating a semiconductor element on a semiconductor substrate having a support substrate and a semiconductor layer above the support substrate. The method includes preparing the semiconductor substrate having a transistor formation region and an element isolation region both defined thereon; forming a pad oxide film on the semiconductor layer of the semiconductor substrate; forming an oxidation-resistant mask layer on the pad oxide film; forming a resist mask to cover the transistor formation region on the oxidation-resistant mask layer; performing a first etching process for etching the oxidation-resistant mask layer using the resist mask as a mask to expose the pad oxide film of the element isolation region; and removing the resist mask and oxidizing the semiconductor layer below the exposed pad oxide film by LOCOS using the exposed oxidation-resistant mask layer as a mask to form an element isolation layer.

Abstract: A diffusion barrier film, a second insulating film, and a cap film are sequentially laminated on a first insulating film over a substrate. A wiring trench portion is formed extending therethrough to the first insulating film, assuming that the ratio of a width of the wiring trench portion in a direction orthogonal to its extending direction to a height of the wiring trench portion is 2.8 times even at a maximum. A barrier metal film is formed to cover the cap film and the wiring trench portion. A wiring film is deposited to cover the barrier metal film. The wiring film and the barrier metal film are chipped away until the surface of the cap film is exposed from the surface of the wiring film, thereby to form a wiring portion which buries the wiring trench portion.

Abstract: A drive of a display panel, according to the invention, comprises first switching means SEGm for changing over between connection of the respective data lines SWsm to the side of respective variable current sources and connection thereof to a grounding side, second switching means SWc2 for changing over a potential of the respective scanning lines between a power supply potential VC and a grounding potential, a drive control circuit for controlling the first switching means and second switching means correspondingly to input data, a comparison circuit provided in each of the data lines, for outputting a control signal by comparing a potential from a voltage regulator with a potential of the respective data lines, and a current control circuit for controlling a current of the variable current source provided in each of the data lines based on results of comparison executed by the respective comparison circuit.

Abstract: A test apparatus for a semiconductor memory device applies a test input pattern to the semiconductor memory device to produce a test output pattern. The test apparatus compares the test output pattern to an expected output pattern using a plurality of comparators to determine whether the semiconductor memory device is defective. The plurality of comparators are respectively controlled by a respective plurality of strobe signals having relative phase delays so that the test output pattern is compared to the expected output pattern at different times.

Abstract: A predetermined syncword detecting circuit includes a matched-bit-number comparing circuit, a comparing-result-change detecting circuit, a detected-result storing circuit, a total number detecting circuit, and a syncword detecting circuit. The matched-bit-number comparing circuit acquires and compares a number of bits in a baseband signal that matches bits of the predetermined syncword with a threshold. The comparing-result-change detecting circuit samples the comparison result, and detects changes in the comparison result. The detected-result storing circuit sequentially stores a result of the comparing-result-change detecting circuit. The total-number detecting circuit detects a total number of the result of the matched-bit-number comparing circuit. The result is included in an N cycle period and surpasses the threshold. The syncword detecting circuit detects the predetermined syncword and selects an intermediate phase of the cycles as a detection phase.

Abstract: A flash memory device and a method of erasing memory cells in a flash memory device are provided. A first post program operation is performed on erased memory cells having a threshold voltage lower than a first program verify voltage. A second post program operation is performed on erased memory cells having a threshold voltage lower than a second program verify voltage. The second program verify voltage is lower than the first program verify voltage.

Abstract: A method of controlling On-Die Termination (ODT) resistors of memory devices sharing signal lines is provided. The ODT controlling method comprises setting an ODT control enable signal of each of the memory devices and address/command or data termination information to a mode register of the corresponding memory device, and controlling resistances of ODT resistors of the signal lines in the memory devices in response to the address/command or data termination information and termination addresses. When only one of the memory devices is activated, ODT resistors of the activated memory device are set to a first resistance. When all the memory devices are activated, ODT resistors of the memory devices are set to a second resistance.

Abstract: A digital camera system has integrated accelerometers for determining static and dynamic accelerations of the digital camera system. Data relating to static and dynamic accelerations are stored with recorded image data for further processing, such as for correcting image data for roll, pitch and vibrations and for displaying recorded images with a predetermined orientation using information about, e.g., roll. Data may also be used on-the-fly for smear suppression caused by vibrations.

Abstract: A semiconductor device with a low drain current in the off-state of LDD type accommodating high voltages is provided. On the thermal oxide film, a polysilicon film and a CVD oxide film, and a resist pattern are formed, then the CVD oxide film is side-etched for formation of a CVD oxide film which is after the etching one-size smaller than the polysilicon film. Using the resist pattern as a mask, an impurity is implanted at a high concentration for formation of a source/drain region at a high concentration in an area which does not overlap with the polysilicon film. Further, the resist pattern is removed, and using the CVD oxide film as a mask, an impurity is implanted at a low concentration for formation of an LDD region of a low concentration in an area which overlaps with the gate electrode of the polysilicon film.

Abstract: In a semiconductor nonvolatile memory, plural first nonvolatile memory cells are arranged in the memory array. Plural memory areas are arranged in the memory array and have plural second nonvolatile memory cells which store the same predetermined information. A sequence circuit generates a memory address, a latch selection signal, and a control signal at predetermined timings when a power is turned on. A write-read unit writes and reads information to and from the memory array and the memory areas based on the memory address and the control signal. A latch circuit latches the predetermined information, read by the write-read unit, based on the latch selection signal. A selection-drive unit selects the first or second nonvolatile memory cells based on the memory address and the predetermined information latched by the latch circuit, and applies a predetermined voltage to drive the selected first or second nonvolatile memory cells.

Abstract: A stackable semiconductor package includes a top package, a bottom package, an adhesive layer, a plurality of wires and a molding compound. A part of a surface of a chip of the bottom package is exposed. The top package is inverted, and is adhered to the chip of the bottom package with the adhesive layer. The wires electrically connect a substrate of the bottom package and a substrate of the top package. The molding compound encapsulates the top package, the bottom package, the adhesive layer,and the wires, and exposes a part of a surface of the substrate of the top package. Thus, the stackable semiconductor package includes at least two chips, thereby increasing the chip density and improving the applicability.

Abstract: A cyclic digital to analog converter (CDAC) in a pipeline structure includes a first CDAC block and a second CDAC block. The first CDAC block receives a first digital signal and converts the first digital signal to a first analog value. The first CDAC block includes a charging capacitor for charging according to the first digital signal and a first storing capacitor for storing the first analog value. The second CDAC block receives a second digital signal and converts the second digital signal to a second analog value. The second CDAC block includes the charging capacitor for charging according to the second digital signal and a second storing capacitor for storing the second analog value. The first CDAC block and the second CDAC block share the charging capacitor.

Abstract: A semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof are provided. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to write data to a cell in the memory cell array and to read data from the cell, and a bypass control unit configured to control a late write operation and a bypass operation of the peripheral circuit according to mode conversion of the semiconductor memory device. Accordingly, data coherency can be maintained. In addition, dummy cycle time that may occur during the mode conversion can be prevented by generating a mode conversion signal only in response to toggling of a clock signal.

Abstract: A track following control apparatus and method for a hard disk drive (HDD) is disclosed and includes an estimator receiving a position error signal from a HDA and generating estimated state information for a magnetic head in response to the position error signal, and a controller receiving the estimated state information and generating a control signal controlling operation of the HAD, wherein the estimator and controller are variably configured according to a write mode or a read mode.

Abstract: A Hard Disk Drive (HDD) and related write control method are disclosed. The write control method includes; detecting a free fall state during a current write operation to a current sector, waiting until completion of the current write operation to the current sector, and thereafter stopping the current write operation and unloading a read/write head performing the current write operation.