Patents Represented by Attorney Volentine & Whitt, P.L.L.C.

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  • Sawing method for a semiconductor element with a microelectromechanical system
    Patent number: 7674688
    Abstract: A sawing method for a Micro Electro-Mechanical Systems (MEMS) semiconductor device, wherein a gum material is disposed between a wafer having at least one MEMS and a carrier, and the gum material is disposed around the MEMS. The wafer is sawed according to the position correspondingly above the gum material. Finally, the carrier and the gum material are removed. By disposing the gum material between the carrier and the wafer, the MEMS are protected, and the wafer and the MEMS can avoid the pollution of water and foreign material, so that the yield can be improved. Furthermore, the wafer is sawed from the backside till the gum material without sawing through the gum material, so that the carrier is not sawed. Therefore, the carrier can be reused, such that the cost is reduced.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: March 9, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Min Hsiao
  • Level shifter
    Patent number: 7675344
    Abstract: A level shifter that prevents through currents thereat, including a holding circuit having an inverter made up of transistors connected between an internal node and a ground potential and an inverter made up of transistors connected between an internal node and the ground potential. These inverters are connected in loop form thereby to hold signals of nodes. Thus, even when input signals complementary to each other originally are both brought to a level “L”, the signals of the nodes are held at the immediately preceding level, thus making it possible to prevent through currents from flowing through the transistors respectively.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: March 9, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Koichi Morikawa
  • Electro-static discharge protection circuit and semiconductor device having the same
    Patent number: 7671415
    Abstract: An electro-static discharge protection circuit and a semiconductor device having the same is disclosed. The electro-static discharge protection circuit has a current control circuit. The current control circuit has a first capacitive element. When the external source voltage is applied to the external source voltage supply line, the booster circuit in the internal circuitry boosts the internal source voltage of the internal source voltage supply line. The external source voltage becomes transiently greater than the internal source voltage at the early stage of the boosting step when the booster circuit boosts the internal source voltage based on the external source voltage.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: March 2, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Toshikazu Kuroda, Hirokazu Hayashi, Yasuhiro Fukuda
  • Image sensor including active pixel sensor array with photoelectric conversion region
    Patent number: 7671314
    Abstract: In one aspect, an image sensor is provided which includes an array of unit active pixels. Each of the unit active pixels comprises a first active area including a plurality of photoelectric conversion regions, and a second active area separated from the first active area. The first active areas are arranged in rows and columns so as to define row and column extending spacings there between, and the second active areas are located at respective intersections of the row and column extending spacings defined between the first active areas.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: March 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Duck-hyung Lee, Kang-bok Lee, Seok-ha Lee
  • Method for fabrication MEMS-resonator
    Patent number: 7666700
    Abstract: The present invention is an etching mask used for fabricating of the MEMS resonator including an oscillator which both edges are fixed to a base substance and vibrates to a vibrating direction, and an electrode which is fixed to a base substance by vibration is impossible in parallel for the oscillator, and is placed every one or more at the both sides of the oscillator. The etching mask includes a mask pattern 36 for oscillators which covers an oscillator formation scheduled region 34 on a conductive film 30 formed all over a sacrificial film which covers a region of the principal surface except both edges of the oscillator, and a mask pattern 40 for electrodes which covers an electrode formation scheduled region 38 on a conductive film.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: February 23, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yasushi Igarashi
  • Process of manufacturing semiconductor device
    Patent number: 7666747
    Abstract: A method that suppresses etching damage without increasing a chip area of a semiconductor device. An integrated circuit including a MOS transistor is formed in a device area, and a discharge diffusion region is formed in a device area, and a discharge diffusion region is formed in a grid area. The discharge diffusion region is connected to a metal wiring of the integrated circuit via a contact hole. Therefore, when the metal wiring is formed by a dry etching method, an electric charge stored in the metal wiring is discharged to a semiconductor substrate through the discharge diffusion region. Thus, etching damage of the MOS transistor is reduced. Since the discharge diffusion region and the contact hole are formed within the grid area, they are cut off by a dicing process, thus causing no increase in chip area of the semiconductor device.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: February 23, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Keisuke Oosawa, Hideyuki Ando
  • Polishing pad having groove structure for avoiding stripping of a polishing surface of the polishing pad
    Patent number: 7662028
    Abstract: A groove structure for avoiding stripping of a polishing surface of a polishing pad, the polishing pad including a base material and a grinding layer. The base material has a surface. The grinding layer is disposed on the surface, and part of the surface around the edge of the base material is exposed. The grinding layer has a plurality of first grooves and second grooves, and the first grooves cross the second grooves to define a plurality of grinding areas. The exposed part of the surface around the edge of the base material is located between the first grooves, the second grooves and the edge of the polishing pad. The polishing pad contains more grinding liquid, to clean the small grinded pieces. The grinding layer does not have an acute structure and is not easily peeled to form the small grinded pieces. Therefore, grinding quality and grinding effect are improved.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: February 16, 2010
    Assignee: Bestac Advanced Material Co., Ltd.
    Inventors: Chung-Chih Feng, Wei-Te Liu, Yung-Chang Hung, Chun-Ta Wang, I-Peng Yao
  • Semiconductor device, semiconductor package for use therein, and manufacturing method thereof
    Patent number: 7663251
    Abstract: A semiconductor package includes a substrate for mounting and fixing a semiconductor chip thereon and a connecting pattern. The substrate is provided with an elongate opening formed therein. The semiconductor chip is fixed with its surface being mounted on the substrate and with its electrode being aligned within the elongate opening. The electrode of the semiconductor chip is electrically connected to the connecting pattern via wires through the elongate opening. The elongate opening and the wires are sealed with resin.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: February 16, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Takaaki Sasaki
  • Semiconductor device for supplying external power supply voltages to three circuit blocks including USB controller and I/O block
    Patent number: 7664969
    Abstract: A semiconductor device includes first, second and third power supply terminals respectively supplied with first, second and third power supply voltages. The semiconductor device also includes a first terminal connectable to a host device and a second terminal connectable to a peripheral device. The semiconductor device also includes a first circuit block connected to the first terminal and the first power supply terminal and receiving data output from the host device based on the first power supply voltage, a second circuit block connected to the second terminal and the third power supply terminal and receiving data output from the peripheral device based on the third power supply voltage, and a third circuit block connected to the second power supply terminal and controlling operation of the first circuit block and the second circuit block based on the second power supply voltage.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: February 16, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Mitsuya Ohie, Kyotaro Nakamura, Shuichi Hashidate
  • Low noise amplifier
    Patent number: 7663441
    Abstract: A low noise amplifier includes a main amplifier configured to amplify a first input signal to generate a first output signal and an auxiliary amplifier configured to amplify a second input signal to generate a second output signal. The auxiliary amplifier is coupled to the main amplifier for superposing the second output signal and the first output signal. The low noise amplifier also includes an adjusting unit configured to adjust a time constant for reducing a third order intermodulation distortion of the superposed signal in response to a control signal. The adjusting unit is configured to generate the second input signal based on the time constant and the first input signal.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: February 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Byoung-Joong Kang
  • Silicon-on-sapphire semiconductor device with shallow lightly-doped drain
    Patent number: 7663189
    Abstract: A semiconductor device is created in a doped silicon layer at most one-tenth of a micrometer thick formed on and having an interface with a sapphire substrate. An oppositely doped source region is formed in the silicon layer. A gate electrode is formed above part of the silicon layer. A diffusion layer doped with the same type of impurity as the source region but at a lower concentration is formed in the silicon layer, extending into a first area beneath the gate electrode, functioning as a drain region or as a lightly-doped extension of a more heavily doped drain region. The depth of this diffusion layer is less than the thickness of the silicon layer. This comparatively shallow diffusion depth reduces current leakage by inhibiting the formation of a back channel.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: February 16, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Koichi Fukuda
  • Image compression for rapid high-quality imaging
    Patent number: 7656561
    Abstract: Lossless, near-lossless, and lossy compression and decompression of digital image data, whereby the image data can be compressed and decompressed on-the-fly with no need for external RAM resources for temporary data storage while compressing/decompressing image data. Implementing the algorithm only requires a very limited amount of silicon and yields very high performance in relation to very low power consumption. The described implementation is optimized for raw image data from a sensor with a Bayer filter pattern but can be used on data from image sensors with ay color filter. The compression algorithm contains a line indexing formation which enables very fast subsampling of an already compressed image and the possibility to decompress only parts of an image—this improves performance and reduces the need for temporary RAM storage greatly when zooming and in postprocessing.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: February 2, 2010
    Assignee: Phase One A/S
    Inventors: Claus Mølgaard, Thomas Alexander Rogon, Thomas Andersen
  • Semiconductor memory device having error correction function
    Patent number: 7656322
    Abstract: A semiconductor memory device configured such that the time required for its access test can be reduced comprising a memory cell array, a row decoder, a column decoder, an error correction circuit, and an output circuit. The error correction circuit performs error correction on a code word read through the bit lines selected by the column decoder from ones of memory cells located at places at which the word line selected by the row decoder and the selected bit lines cross over, thereby detecting an error position in the code word to generate error detection data indicating the error position and corrects the information bit in the detected error position to generate error corrected data. The output circuit relays to the outside the error corrected data when a normal operation mode has been designated and the error detection data when a test operation mode has been designated.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: February 2, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Daisuke Oda
  • Memory using packet controller and memory
    Patent number: 7657713
    Abstract: A memory that includes a plurality of packet pins, a synchronous memory, and a packet controller. The synchronous memory receives address and control signals in synchronization with a clock signal. The packet controller sequentially receives packet data bits through the packet pins in synchronization with the clock signal when a packet enable signal is activated, and converts the inputted packet data into the address and control signals. Specifically, packet data bits that are first inputted through the packet pins represent an operation mode.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: February 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bok-Gue Park, Dong-Il Seo, Hyun-Soon Jang, Woo-Seop Jeong
  • ESD protection device
    Patent number: 7649229
    Abstract: A semiconductor device capable of preventing an electrostatic surge without increasing a leak current. In the semiconductor device, a protection circuit for protecting an internal circuit is provided between a source line and a ground line. The protection circuit has a protection transistor of which the drain is connected to the source line and the source and gate are connected to the ground line. The protection transistor is configured by integrally forming two types of transistor structural portions. The latter of the transistor structural portions is longer than the former thereof in gate length. In addition, the sum of gate widths of the latter transistor structural portions is larger than the sum of gate widths of the former transistor structural portions.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: January 19, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Katsuhiro Kato
  • Semiconductor device, stacked structure, and manufacturing method
    Patent number: 7649249
    Abstract: An array of electrically conductive members, formed around the edges of a semiconductor device or chip, penetrate from one major surface of the device to the other major surface. In an area located inward of this array, a multiplicity of thermally conductive members also penetrate from one major surface to the other major surface. The semiconductor device can be manufactured from a semiconductor wafer by creating holes that penetrate partway through the wafer, filling the holes with metal to form the electrically conductive members and thermally conductive members, and then grinding the lower surface of the wafer to expose the ends of the electrically conductive members and thermally conductive members before dicing the wafer into chips. The thermally conductive members improve heat dissipation performance when semiconductor chips of this type are combined into a stacked multichip package.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: January 19, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Takashi Noguchi
  • Three-dimensional package and method of making the same
    Patent number: 7642132
    Abstract: The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: January 5, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Min-Lung Huang, Wei-Chung Wang, Po-Jen Cheng, Kuo-Chung Yee, Ching-Huei Su, Jian-Wen Lo, Chian-Chi Lin
  • Reference current generator circuit
    Patent number: 7638996
    Abstract: A reference current generator circuit that suppresses variations in the production of parts and attains a voltage reduction, thereby suppressing power consumption. The reference current generator circuit includes current generating circuit parts, differential amplifying circuit parts, output circuit parts that output first and second reference currents respectively, and a resistor for converting a reference current to a reference voltage. Since respective voltages are kept at the same potential, respective PMOSs are operated in a linear region by means of the differential amplifying circuit pads.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: December 29, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Naoaki Sugimura, Danya Sugai
  • Semiconductor integrated circuit
    Patent number: 7639036
    Abstract: A semiconductor integrated circuit having a test circuit for inspecting states of connections between a plurality of pads and respective external terminals by bonding wires. The test circuit comprises, for each of a plurality of pads, a control terminal provided to receive a control signal of a logic level equal to the logic level of a signal applied to a corresponding one of the external terminals, an inverter which inverts the logic level on the control terminal, an inverted output terminal of the inverter being connected to the pad via a connection line; and an exclusive-NOR gate which outputs an exclusive NOR of the logic level on the connection line and the logic level on the control terminal.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: December 29, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Akira Akahori
  • Three-dimensional package and method of making the same
    Patent number: 7635917
    Abstract: The present invention relates to a three-dimensional package and method of making the same. The package includes a first substrate, a first chip, a second substrate, a second chip, a spacer, and a first molding compound. The first chip is electrically connected to the first substrate. The second substrate is electrically connected to the first substrate. The second chip is electrically connected to the second substrate. One end of the spacer is attached to the first chip, and the other end of the spacer is attached to the second chip. The first molding compound encapsulates the first substrate, the first chip, the second substrate, the second chip, and the spacer. In the present invention, the adhesion between the spacer and the second chip is enhanced, and the overall thickness of the three-dimensional package is reduced.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: December 22, 2009
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ching-Chun Wang, Yen-Yi Wu, Sem-Wei Lin