Patents Represented by Attorney, Agent or Law Firm W. Douglas Carothers, Jr.
  • Patent number: 5448132
    Abstract: An array field emitter device utilizes field emission devices disposed in a matrix or array each comprising an opening in an insulating layer with an upwardly extended cathode with a tip disposed centrally within the opening and a gate electrode substantially concentric with each the cathode tip and having a lip extending into the opening forming a downwardly descending lip projection. Such an array display device can be of the multiplex driven type or can be of the active matrix type.
    Type: Grant
    Filed: September 30, 1993
    Date of Patent: September 5, 1995
    Assignee: Seiko Epson Corporation
    Inventor: Hiroshi Komatsu
  • Patent number: 5428242
    Abstract: A semiconductor device provides for shielding of resistance elements as well as other elongated passive or active components formed in the structure by diffusion of impurities into a polycrystalline silicon layer or a semiconductor substrate and a conductor is formed on an upper surface of the resistance element having a resistance value lower than that of the formed resistance element. Also, the conductor is formed so as to hold a fixed potential value. This structure prevents an invasion or infiltration of impurities which causes a variation in the resistance value of the resistance element. Further, the conductor functions as shielding from noise from a signal line in close proximity to the resistance element or from external noise by means of fixing the conductor at a fixed potential value thereby maintaining the stability of the resistance value of the resistance element.
    Type: Grant
    Filed: October 23, 1992
    Date of Patent: June 27, 1995
    Assignee: Seiko Epson Corporation
    Inventors: Yasunari Furuya, Kazuko Moriya
  • Patent number: 5428714
    Abstract: A computer system is connected to a printer via a parallel interface, for point-of-sale (POS) applications employing one or more different paper sources, such as, continuous tape, document insertion, and sheet validation. A detector is associated with each paper source to sense a paper empty or out condition. The printer has an addressable latch that enables a choice of one or more of these detectors for connection through to a single status line within the parallel printer interface. The computer CPU can access the addressable latch prior to any printing so that the presence of an appropriate type of paper in its appropriate print position in the printer can be checked or tested utilizing an industry standard parallel printer interface, such as, the widely employed Centronics interface.
    Type: Grant
    Filed: October 29, 1991
    Date of Patent: June 27, 1995
    Assignee: Seiko Epson Corporation
    Inventors: Kazunari Yawata, Torao Yajima, Takuya Hyonaga, Yoshikazu Ito, Hiroshi Ono, Kazuhisa Aruga, Noboru Yanagisawa
  • Patent number: 5427641
    Abstract: A tape carrier for electronic components is provided with enlarged regions along cut out lines defining the boundaries of the electronic component mount area. Provision is made for temporarily maintaining the cut out mount area substantially coplanar with remaining portions of the tape carrier. In the preferred embodiment, this is accomplished by way of an adhesive tape bridging the enlarged openings or by tabs or micro connectors bridging the enlarged openings. Thereafter, the mounts can be totally removed from the carrier film by severing the tape or the tabs. The enlarged regions facilitate the severance of the tape or tabs in an automated assembly line environment.
    Type: Grant
    Filed: October 19, 1993
    Date of Patent: June 27, 1995
    Assignee: Seiko Epson Corporation
    Inventors: Eiji Muramatsu, Masaru Kamimura
  • Patent number: 5412285
    Abstract: One embodiment of the present invention is a linear amplifier based on a field emission device that is driven at its input in current-mode. The ratio (gamma) of the separation distance between the anode and cathode (d.sub.ak) to the separation distance between the cathode and gate (d.sub.gk) is in the range of 20 to 200. The amplifier betas that result from these gammas range from a low of 30 to a high of 1000. The linear amplifier is combined with an active matrix to form a vacuum flat-panel display with good gray-scale performance.
    Type: Grant
    Filed: June 3, 1993
    Date of Patent: May 2, 1995
    Assignee: Seiko Epson Corporation
    Inventor: Hiroshi Komatsu
  • Patent number: 5410641
    Abstract: The image processing performance of a present day or existing page printer, e.g., electrophotographic printer, is improved and accelerated with the use of a detachable intelligent cartridge which contains a CPU and necessary memory to process print data into image dated for the electronic control unit of the printer to which the cartridge is attached. Depending upon the page description language (PDL) to be employed, a cartridge can be selected for use with the printer and accelerate its PDL conversion and printing output. The intelligent cartridge CPU, which is different from the printer CPU, receives print data from the printer and, since the data bus connecting the intelligent cartridge and the electronic control unit of the printer has only a read only capability from the electronic control unit, data transfer to the cartridge is made possible by utilizing the print data as an index for the read address accomplished by the printer CPU.
    Type: Grant
    Filed: December 30, 1991
    Date of Patent: April 25, 1995
    Assignee: Seiko Epson Corporation
    Inventors: Kenichi Wakabayashi, Kaoru Hatakoshi, Kiyotaka Nishimura, Tsuyoshi Morikawa, Tadashi Shiozaki, Akira Nakajima, Hajime Nishizawa, Chitoshi Takayama
  • Patent number: 5404043
    Abstract: A sidewall construction is utilized in the fabrication of semiconductor devices comprising planar type bipolar transistors wherein the width of the sidewall construction can be accuracy controlled which, in turn, controls accuracy the channel length of the base of the planar type bipolar transistors. This technique provides ways of preventing short circuiting between the formed transistor collector and emitter regions of the planar type bipolar transistors. The sidewall construction can also be employed in fabrication combination planar type bipolar/MIS type transistors resulting in higher density of these structures over the prior art laterally positioned structures.
    Type: Grant
    Filed: October 20, 1993
    Date of Patent: April 4, 1995
    Assignee: Seiko Epson Corporation
    Inventor: Toshihiko Higuchi
  • Patent number: 5398305
    Abstract: A printer control device is employed with host computer controlled printers, typically of the point-of-sale (POS) type, which are capable of printing on several different types of recording paper. Several detectors are used on the printer to sense out-of-paper conditions with at least one detector being associated with each paper source used, and a detector selection device is used to determine which detector outputs are to be connected to the host computer through a communications interface. Detector output values can be stored and logically combined to allow transfer over a single communications line. Specific detector outputs can be enabled or selected for transfer to the host or for use in termination of printing operations. A paper type selector is used for setting line spacing or advancement amounts which are stored by the printer controller for later retrieval. Typically each advancement value relative to one type of paper is stored separately in a memory location or element.
    Type: Grant
    Filed: May 14, 1993
    Date of Patent: March 14, 1995
    Assignee: Seiko Epson Corporation
    Inventors: Kazunari Yawata, Torao Yajima, Takuya Hyonaga, Yoshikazu Ito, Hiroshi Ono, Kazuhisa Aruga, Noboru Yanagisawa, Mitsuaki Teradaira
  • Patent number: 5396353
    Abstract: An opto-electrical apparatus, such as, a liquid crystal display device, comprises a pixel electrode driving element a first conductor, an insulator and a second conductor formed in stacked sequence on the substrate with the insulator comprising a thicker barrier layer atop the first conductor compared to the side portions thereof. The second conductor is formed in two locations on the insulating side portions of the insulator as well as a portion of the top surface comprising the barrier layer. As a result, a pair of nonlinear devices are formed relative to the same insulator and are connected between a pixel electrode and inter-device interconnect so that an electrically aligned, series connected pair of MIM devices with opposite polarity formation both having nonlinear current/voltage characteristics.
    Type: Grant
    Filed: June 24, 1992
    Date of Patent: March 7, 1995
    Assignee: Seiko Epson Corporation
    Inventors: Kotoyoshi Takahashi, Takeyoshi Ushiki
  • Patent number: 5389191
    Abstract: A mounting apparatus for deploying a plurality of FPC tape carrier electronic component mounting structures having a plurality of cut out regions in a FPC tape carrier formed spatially along the length thereof, which regions define electronic component mounts. These cut out regions are contained within the confines of the FPC tape carrier and having a preformed substantially closed loop cut out boundary. Each of these cut out regions may contain at least one electronic component mount having a semiconductor integrated circuit chip electronic device electrically connected to at least one lead pattern formed on the carrier within the cut out region boundary. Slits or slit apertures are formed at one or more points along the cut out boundary. Securing attachment is provided at one or more points along the mount boundary, which are provided at the regions of the slits or slit apertures to secure the electronic component mounts with minimal connection to the body of the tape carrier.
    Type: Grant
    Filed: October 13, 1993
    Date of Patent: February 14, 1995
    Assignee: Seiko Epson Corporation
    Inventors: Eiji Muramatsu, Masaru Kamimura
  • Patent number: 5376435
    Abstract: An interlayer dielectric structure for microelectronic devices having multiple conducting layers provides a planarized surface for deposition of subsequent layers and further prevents cracking of spin-on-glass by limiting spin-on-glass thickness to about 0.4 .mu.m or less. A first dielectric layer is formed over a first conducting layer by means of reacting Si(OC.sub.2 H.sub.5).sub.4 and O.sub.2 at approximately 9 torr between 370.degree. C. to 400.degree. C., and a second dielectric layer is formed over the first dielectric layer by a method different than that used to form the first dielectric layer. After etching back the second dielectric layer, a spin-on-glass layer is formed. Spin-on-glass layer is etched back to provide a planar surface and a third dielectric-layer is formed over the spin-on-glass layer. The resulting surface is ready for contact hole formation, deposition and patterning of subsequent conductive and insulating layers.
    Type: Grant
    Filed: July 16, 1993
    Date of Patent: December 27, 1994
    Assignee: Seiko Epson Corporation
    Inventor: Yukio Morozumi
  • Patent number: 5375133
    Abstract: A surface emitting semiconductor laser is provided with at least reflection mirrors on the substrate side composed of a first layer that is made of a Group III-V compound semiconductor and a second layer that is made of a Group III-V compound semiconductor with an energy bandgap that is larger than that of the first layer. The first and second layers are alternately stacked. The semiconductor laser is also composed of a distributive reflection multiple layer mirror that has an interface region between first and second layers having a carrier concentration that is higher than that of other regions. As a result, the multiple layer band structure of the distributive reflection mirror has been improved, current easily flows vertically through the multiple layers and the element resistance is low.
    Type: Grant
    Filed: March 3, 1994
    Date of Patent: December 20, 1994
    Assignee: Seiko Epson Corporation
    Inventors: Katsumi Mori, Tatsuya Asaka, Hideaki Iwano
  • Patent number: 5365257
    Abstract: A thermal printer drive control apparatus of the type having a thermal print head comprising a plurality of heating elements provides for reliable cost effective thermal head temperature detection by means of producing multiple, different current flow intervals that are applied to binary data to produce data drive signals for the heating elements. The current flow intervals are based upon historical drive data derived from linear temperature conditions sensed at the thermal print head. This information is converted to a digitized representation for use in conjunction with a table placed in memory that provides predetermined current flow intervals based upon the digitized representation. Further, circuitry is provided to produce heating element drive signals having pulse widths based upon the determined current flow intervals.
    Type: Grant
    Filed: July 22, 1993
    Date of Patent: November 15, 1994
    Assignee: Seiko Epson Corporation
    Inventors: Masahiro Minowa, Naoki Kobayashi, Satoshi Nakajima, Tadashi Furuhata
  • Patent number: 5363500
    Abstract: A system for improving access time to video display data uses a shadow memory having fewer storage locations than a display memory. The shadow memory and the display memory share a set of addresses such that data written to the display memory, at an address shared by the shadow memory, is identically written to the shadow memory. Read requests directed to the display memory result in: (a) data returned from the shadow memory when access to a shared address is requested, and (b) data returned from the display memory when access to a non-shared address is requested.
    Type: Grant
    Filed: January 24, 1991
    Date of Patent: November 8, 1994
    Assignee: Seiko Epson Corporation
    Inventor: Koji Takeda
  • Patent number: 5361151
    Abstract: A reflection-type liquid crystal (LC) device having a twisted nematic (TN) LC layer that lets linearly-polarized incident light enter and become circularly-polarized at a reflecting surface, and then linearly polarizes it, after reflecting, with a plane of polarization that has been rotated 90.degree. from the incident light at an light output surface. The TN LC layer allows linearly-polarized incident light to enter at an angle to the molecular plane of light input of the twisted nematic LC, and to linearly polarize the light after reflection. The plane of polarization is rotated 90.degree. from the incident light at the light output surface. The TN LC layer also allows circularly-polarized incident light to enter and become linearly-polarized light at the reflecting surface. Circularly-polarized light after reflection may be rotated opposite the incident circularly-polarized light at the light output surface to provide for reverse on/off states.
    Type: Grant
    Filed: October 7, 1993
    Date of Patent: November 1, 1994
    Assignee: Seiko Epson Corporation
    Inventors: Tomio Sonehara, Osamu Okumura
  • Patent number: 5349206
    Abstract: An integrated circuit with high density load elements in memory cells forming a memory array wherein the load elements are either of the active (e.g., TFTs) or passive (e.g., resistance) type and designed so that the connection path between these elements and active element domains is extended to be longer within the same or smaller scale of the memory cell configuration. For this purpose, the connection path may be made to meander to provide for greater length, i.e., extend in one direction and then another within a single memory cell configuration. This further creates additional space for extending the resistance value of the active or passive load element which, in turn, permits a reduction in drain current, i.e., current consumption, during operational conditions of the memory cells or other circuits.
    Type: Grant
    Filed: April 20, 1992
    Date of Patent: September 20, 1994
    Assignee: Seiko Epson Corporation
    Inventor: Masakazu Kimura
  • Patent number: 5336000
    Abstract: A thermal transfer type printer having an ink sheet rejuvenation system and method for rejuvenation of an ink sheet used in the printer wherein the printer has a transport path for transporting the ink sheet past an ink deposition station for selective transfer of powder ink from a powder ink supply to an ink sheet surface when a bias is applied at the station; ink fixing station having fixing applicator for selective engagement with the ink sheet surface for fixing the powder ink to the ink sheet; and a printing station having a thermal print head for engagement of the print head with the ink sheet onto a surface of an output medium for forming images on the output medium by selective thermal transfer of ink to the output medium surface in imagewise formation.
    Type: Grant
    Filed: June 1, 1993
    Date of Patent: August 9, 1994
    Assignee: Seiko Epson Corporation
    Inventors: Tsuneo Handa, Noriyoshi Chiba, Masanao Kunugi
  • Patent number: 5327011
    Abstract: A semiconductor device has an interconnect layer, connected to a connecting region, such as a diffusion region or layer formed on the surface of a substrate, through a contact hole formed in an interlayer insulating film, which includes a concavity, representing a defective portion, extending from the bottom portion of the contact hole to the surface of the interconnect layer. This defective portion occurs because the metal comprising the interconnect layer will not penetrate to completely fill the contact hole. To correct for this formed defective portion, the concavity, the concavity is permitted to be formed followed by its filling with a plug electrode comprising a high quality penetration metal film, such as, tungsten. As a result, the mechanical as well as electrical characteristics of the interconnect layer connection to the connecting region is significantly improve by the presence of the plug electrode.
    Type: Grant
    Filed: July 22, 1992
    Date of Patent: July 5, 1994
    Assignee: Seiko Epson Corporation
    Inventor: Seiichi Iwamatsu
  • Patent number: 5319320
    Abstract: The frequency control and phase control of a voltage-controlled oscillator (50) of a phase-locked loop (100) comprise two current paths. The frequency control system comprises a filter (75) that converts pulse output current (i.sub.1) of a charge pump (70) generated by phase error signals (X.sub.1, X.sub.2) to a DC voltage, and a resistor (R.sub.1 or R.sub.2) that converts that voltage to DC current (i.sub.3), and the phase control system comprises a charge pump (80) that generates a pulse output current (i.sub.2) using the phase error signals (X.sub.1, X.sub.2). The frequency and phase of the oscillator output (V.sub.OUT) of the voltage-controlled oscillator (50) is controlled by a composite current i.sub.4, which is the sum of the DC current (i.sub.3) and the output current i.sub.2. Since it is possible to make the natural angular frequency proportional to the data transfer rate while the damping factor remains unchanged, by changing the value of the currents (i.sub.3, i.sub.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: June 7, 1994
    Assignee: Seiko Epson Corporation
    Inventors: Akira Abe, Takeshi Kawasaki
  • Patent number: 5305126
    Abstract: A polymer dispersed liquid crystal material (PDLC) device is fabricated by sealing a composite layer mixture of components comprising a polymer and liquid crystal material while both are in their liquid phase in a gap portion formed between two substrates of the device. A predetermined directional alignment is transmitted to the polymer via the liquid crystal material by means, for example, of formed directional alignment on surfaces in contact with the composite layer, such as, by deposited alignment films on a surface of at least one of the substrates. The predetermined directional alignment of the polymer is thereafter fixed by means of a polymer hardening method, such as, for example, by polymerization of a polymer precursor, so that the predetermined directional alignment of the polymer is permanently retain within the liquid crystal material, i.e., the polymer is in a solid phase and the liquid crystal material remains in its liquid phase.
    Type: Grant
    Filed: November 26, 1991
    Date of Patent: April 19, 1994
    Assignee: Seiko Epson Corporation
    Inventors: Hidekazu Kobayashi, Kiyohiro Samizu, Jin-Jei Wu