Patents Represented by Attorney W. Douglas Carothers
  • Patent number: 7060517
    Abstract: A method for reducing insertion loss in a transition region between a plurality of input or output waveguides to a free space coupler region in a photonic integrated circuit (PIC) includes the steps of forming a passivation layer over the waveguides and region and forming the passivation overlayer such that it monotonically increases in thickness through the transition region to the free space coupler region.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: June 13, 2006
    Assignee: Infinera Corporation
    Inventors: Charles H. Joyner, Mark J. Missey, Radhakrishnan L. Nagarajan, Fred A. Kish, Jr.
  • Patent number: 7062114
    Abstract: A photonic integrated circuit (PIC) chip with a plurality of electro-optic components formed on a major surface of the chip and a submount that includes a substrate that extends over the major surface of the chip forming an air gap between the substrate and the major surface, the substrate to support electrical leads for electrical connection to some of the electro-optic components on the chip major surface.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: June 13, 2006
    Assignee: Infinera Corporation
    Inventors: Jonas Webjorn, Robert Grencavich, Vinh D. Nguyen, Donald J. Pavinski, Jr.
  • Patent number: 7058246
    Abstract: A monolithic photonic integrated circuit (PIC) chip comprises an array of modulated sources providing a plurality of channel signals of different wavelengths and an optical combiner coupled to receive the channel signals and produce a combined output of the channel signals. The arrays of modulated sources are formed as ridge waveguides to enhance the output power from the respective modulated sources so that the average output power from the sources is approximately 2 to 4 times higher than in the case of comparable arrays of modulated sources formed as buried waveguides.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: June 6, 2006
    Assignee: Infinera Corporation
    Inventors: Charles H. Joyner, Fred A. Kish, Jr., Frank H. Peters, Atul Mathur, David F. Welch, Andrew G. Dentai, Damien Lambert, Richard P. Schneider, Mark J. Missey
  • Patent number: 7058248
    Abstract: A C- and/or L-band booster optical amplifier is utilized in an optical communication system at the output of one or more semiconductor transmitter photonic integrated circuit (TxPIC) chips or the optical combined outputs of multiple semiconductor transmitter photonic integrated circuit (TxPIC) chips employed in an optical communication module, the deployment of integrated semiconductor optical amplifiers (SOAs) on the TxPIC chips can be eliminated. This would reduce both the complexity in designing and fabricating these chips as well as reducing the power consumption of the TxPIC chips. The deployment of such a Tx booster optical amplifier would also take into consideration the nonlinear effects of difficult high loss single mode fiber (SMF) or other fiber type links by allowing a higher power per channel to be achieved compared to the case where channel amplification is attempted solely on the TxPIC chip.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: June 6, 2006
    Assignee: Infinera Corporation
    Inventors: Stephen G. Grubb, Matthew L. Mitchell, Robert B. Taylor, Ting-Kuang Chiang, Vincent G. Dominic
  • Patent number: 7058263
    Abstract: An optical transport network comprises a monolithic transmitter photonic integrated circuit (TxPIC) InP-based chip and a monolithic receiver photonic integrated circuit (RxPIC) InP-based chip.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: June 6, 2006
    Assignee: Infinera Corporation
    Inventors: David F. Welch, Radhakrishnan L. Nagarajan, Fred A. Kish, Jr., Mark J. Missey, Vincent G. Dominic, Atul Mathur, Frank H. Peters, Charles H. Joyner, Richard P. Schneider, Ting-Kuang Chiang
  • Patent number: 7050666
    Abstract: An optical receiver photonic integrated circuit (RxPIC) system includes a monolithic semiconductor chip having an input to receive a WDM combined channel signal comprising a plurality of optical channel signals of different wavelengths. A chip-integrated decombiner is coupled to the chip input to receive the WDM combined channel signal and separate the same into a plurality of different channel signals having different wavelengths. An array of integrated photodetectors, also integrated on the chip, each receive a separated channel signal and together provide a plurality of electrical signals representative of the optical channel signals. An electronic amplifier receives and amplifies the electrical signals. An electronic dispersion equalization (EDE) circuit is coupled to receive and adjust the amplified electrical signals for timing errors due to imperfect clock recovery of said electrical signals. An clock and data recover (CDR) circuit recovers a signal clock and data signals from the electrical signals.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: May 23, 2006
    Assignee: Infinera Corporation
    Inventors: David F. Welch, Vincent G. Dominic, Ting-Kuang Chiang
  • Patent number: 7043109
    Abstract: A method of in-wafer testing is provided for a monolithic photonic integrated circuit (PIC) formed in a semiconductor wafer where each such in-wafer circuit comprises two or more integrated electro-optic components, one of each in tandem forming a signal channel in the circuit. The method includes the provision of a first integrated photodetector at a rear end of each signal channel and a second integrated photodetector at forward end of each signal channel. Then, the testing is accomplished, first, by sequentially operating a first of a selected channel electro-optic component in a selected circuit to monitor light output from a channel via its first corresponding channel photodetector and adjusting its operating characteristics by detecting that channel electro-optic component output via its second corresponding channel photodetector to provide first calibration data.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: May 9, 2006
    Assignee: Infinera Corporation
    Inventors: Fred A. Kish, Jr., Charles H. Joyner, Mark J. Missey, Frank H. Peters, Radhakrishnan L. Nagarajan, Richard P. Schneider
  • Patent number: 7039075
    Abstract: A semiconductor laser, such as a vertical cavity, surface emitting laser (VCSEL) is coupled to an optical fiber. The other end of the optical fiber has a reflector, so as to provide a fiber-extended cavity for the VCSEL. Such a construction is useful for providing modal stability to the VCSEL or for forming a mode-locked VCSEL. The optical fiber may be a graded index fiber. In such a case, the fiber length may be selected to have an integral number of quarter pitch lengths. The fiber may be doped with an excitable species and lies within a fiber laser cavity. A semiconductor laser may pump the fiber laser, yielding an emission wavelength beyond the scope of the conventional semiconductor laser.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: May 2, 2006
    Inventor: Robert L. Thornton
  • Patent number: 7027703
    Abstract: A method for forming and apparatus comprising a free space coupler region having a plurality of optical waveguides coupled to the space coupler region at an interface region, the waveguides converging with one another to the interface region, and a trench formed between adjacent waveguides, the depth of the trench or trenches extending from an outer point to the interface region and monotonically decreasing in depth from the outer point to the interface region.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: April 11, 2006
    Assignee: Infinera Corporation
    Inventors: Charles H. Joyner, Mark J. Missey, Radhakrishnan L. Nagarajan, Frank H. Peters, Mehrdad Ziari, Fred A. Kish, Jr.
  • Patent number: 7016571
    Abstract: An arrayed waveguide grating (AWG) comprises at least two free space regions, a plurality of grating arms extending between the two space regions, a passivation layer formed over the arrayed waveguide grating and a plurality of inputs at least to one of the free space regions to receive a plurality of channel signals separated by a predetermined channel spacing. A depth of the passivation layer chosen by providing a TE to TM wavelength shift between TE and TM modes propagating through the arrayed waveguide grating being approximately less than or equal to 20% of a magnitude of the channel spacing.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: March 21, 2006
    Assignee: Infinera Corporation
    Inventors: Charles H. Joyner, Mark J. Missey, Radhakrishnan L. Nagarajan, Fred A. Kish, Jr.
  • Patent number: 7010185
    Abstract: A method of deploying a passive optical combiner that is a broad bandwidth spectral wavelength combiner for combining the outputs from multiples transmitter photonic integrated circuit (TxPIC) chips and, thereafter, the amplification of the combined channel signals with a booster optical amplifier couple between the passive optical combiner and the fiber transmission link. The booster optical amplifier may be a rear earth fiber amplifier, such as an erbium doped fiber amplifier (EDFA), or one or more semiconductor optical amplifiers (SOAs) on one or more semiconductor chips.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: March 7, 2006
    Assignee: Infinera Corporation
    Inventors: Stephen G. Grubb, Matthew L. Mitchell, Robert B. Taylor, Ting-Kuang Chiang, Vincent G. Dominic
  • Patent number: 7006719
    Abstract: Disclosed are apparatus and methods of reducing insertion loss, passivation, planarization and in-wafer testing of integrated optical components and in-wafer chips in photonic integrated circuits (PICs).
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: February 28, 2006
    Assignee: Infinera Corporation
    Inventors: Charles H. Joyner, Mark J. Missey, Radhakrishnan L. Nagarajan, Frank H. Peters, Mehrdad Ziari, Fred A. Kish, Jr.
  • Patent number: 6999489
    Abstract: A method of electrically isolating and operating electro-optical components integrated in a monolithic semiconductor photonic chip, such as an EML or PIC chip. A bias, VC, is applied to the isolation region so that any parasitical current path developed between adjacent active or passive optical components, now separated by an isolation region, is established through the electrical isolation region and clamped to the bias, VC. The applied bias, VC, may be a positive bias, a negative bias, or a zero or a ground bias. The electrical isolation regions are formed by spatial current blocking regions formed at adjacent sides of the electrical isolations region transverse to a direction of light propagation through the optical components, or between the electrical isolation regions and adjacent optical components. The spatial current blocking regions may be comprised of a pair of spatially disposed trenches or ion implanted regions or high resistance implanted regions.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: February 14, 2006
    Assignee: Infinera Corporation
    Inventor: Frank H. Peters
  • Patent number: 6985648
    Abstract: A method of in-wafer testing is provided for a monolithic photonic integrated circuit (PIC) formed in a semiconductor wafer where each such in-wafer circuit comprises two or more integrated electro-optic components, one of each in tandem forming a signal channel in the circuit. The method includes the provision of a first integrated photodetector at a rear end of each signal channel and a second integrated photodetector at forward end of each signal channel. Then, the testing is accomplished, first, by sequentially operating a first of a selected channel electro-optic component in a selected circuit to monitor light output from a channel via its first corresponding channel photodetector and adjusting its operating characteristics by detecting that channel electro-optic component output via its second corresponding channel photodetector to provide first calibration data.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: January 10, 2006
    Assignee: Infinera Corporation
    Inventors: Fred A. Kish, Jr., Mark J. Missey, Radhakrishnan L. Nagarajan, Frank H. Peters, Richard P. Schneider, Charles H. Joyner
  • Patent number: 6921925
    Abstract: In photonic integrated circuits (PICs) having at least one active semiconductor device, such as, a buried heterostructure semiconductor laser, LED, modulator, photodiode, heterojunction bipolar transistor, field effect transistor or other active device, a plurality of semiconductor layers are formed on a substrate with one of the layers being an active region. A current channel is formed through this active region defined by current blocking layers formed on adjacent sides of a designated active region channel where the blocking layers substantially confine the current through the channel. The blocking layers are characterized by being an aluminum-containing Group III-V compound, i.e., an Al-III-V layer, intentionally doped with oxygen from an oxide source. Also, wet oxide process or a deposited oxide source may be used to laterally form a native oxide of the Al-III-V layer.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: July 26, 2005
    Inventors: Fred A. Kish, Jr., Sheila K. Mathis, Charles H. Joyner, Richard P. Schneider
  • Patent number: 6922423
    Abstract: A control system architecture that allows a semiconductor laser to be stabilized with respect to critical parameters, such as output power and/or emission wavelength, with a reduced cost with respect to the components required to implement control, while simultaneously maintaining or increasing precision of the control function. This is achieved using sophisticated integrated circuitry contained within the laser package to measure data related to multiple laser operation parameters and to transmit these parameters to a control circuit. In particular, precision thermal measurements may be used to eliminate the need for optical detectors in the laser package. The invention described herein has significant utility for different types of semiconductor lasers, including both edge emitting and VCSEL-type semiconductor lasers.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: July 26, 2005
    Inventor: Robert L. Thornton
  • Patent number: 6922422
    Abstract: Photonic integrated circuits (PIC) semiconductor chips are provided with thermal isolation and/or heat dissipation structures between integrated optical components in the PIC chip, particularly integrated active optical components. These structures may also serve as a ground path for electrical circuitry on the PIC chip. An important function is the enhanced thermal isolation from, or dissipation of heat from, between adjacent or neighboring optical components in the PIC so that required spacing between adjacent optical components can be made even less than the thickness of the substrate thereby realizing a more compact optical component array on the monolithic PIC chips.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: July 26, 2005
    Inventors: Frank H. Peters, Radhakrishnan L. Nagarajan
  • Patent number: 6891202
    Abstract: An active semiconductor device, such as, buried heterostructure semiconductor lasers, LEDs, modulators, photodiodes, heterojunction bipolar transistors, field effect transistors or other active devices, comprise a plurality of semiconductor layers formed on a substrate with one of the layers being an active region. A current channel is formed through this active region defined by current blocking layers formed on adjacent sides of a designated active region channel where the blocking layers substantially confine the current through the channel. The blocking layers are characterized by being an aluminum-containing Group III-V compound, i.e., an Al-III-V layer, intentionally doped with oxygen from an oxide source. Also, wet oxide process or a deposited oxide source may be used to laterally form a native oxide of the Al-III-V layer. An example of a material system for this invention useful at optical telecommunication wavelengths is InGaAsP/InP where the Al-III-V layer comprises InAlAs:O or InAlAs:O:Fe.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: May 10, 2005
    Assignee: Infinera Corporation
    Inventors: Fred A. Kish, Jr., Sheila K. Mathis, Charles H. Joyner, Richard P. Schneider
  • Patent number: 6771682
    Abstract: Electrical isolation regions are formed between adjacently disposed electro-optical components integrated in a monolithic semiconductor photonic chip, such as an EML or PIC chip. A bias, VC, is applied to the isolation region so that any parasitical current path developed between adjacent active or passive optical components, now separated by an isolation region, is established through the electrical isolation region and clamped to the bias, VC. The applied bias, VC, may be a positive bias, a negative bias, or a zero or a ground bias. The electrical isolation regions are formed by spatial current blocking regions formed at adjacent sides of the electrical isolations region transverse to a direction of light propagation through the optical components, or between the electrical isolation regions and adjacent optical components. The spatial current blocking regions may be comprised of a pair of spatially disposed trenches or ion implanted regions or high resistance implanted regions.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: August 3, 2004
    Assignee: Infinera Corporation
    Inventor: Frank H. Peters
  • Patent number: 6707589
    Abstract: An optical modulator drive circuit provides a different approach to driving an optical modulator than presently employed, resulting in a reduction in power dissipation of the drive circuit by as much as 80%. Therefore, this invention dissipates as little as 20% of power of the present drive circuits known in the art. The optical modulator may be a semiconductor electro-absorption modulator but the principle of the invention can be applied any other type of electro-optic modulator that relies on a voltage to modulate an optical signal.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: March 16, 2004
    Assignee: Infinera Corporation
    Inventors: Jeffrey S. Bostak, Ting-Kuang Chiang