Abstract: A data processing apparatus which uses a register file to provide a faster alternative to indirect memory addressing. A functional unit is connected to a data register file (76) which comprises a plurality of registers, each of which is accessed by a corresponding register number. The functional unit (e.g., A-unit 78) can execute at least one indirect register access instruction that comprises an operand register number field. Instruction decode circuitry, connected to the register file and the functional unit, is responsive to the indirect register access instruction to recall data stored in an operand register (190) specified by the operand register number in the instruction, identify the recalled data as a register access number, and recall operand data from a data register corresponding to the register access number for use as an operand by the functional unit.

Abstract: A trigger signal TRIG[0] is produced for use in debugging data processor (14) operations. The trigger signal can be generated in response to event information indicative of events associated with operations of the data processor and further in response to past behavior of a trigger signal. A plurality of intermediate terms index into a look up table loaded from a trigger builder control register. The look up table output is ANDed with output enable signals to produce plural trigger output signals.

Abstract: According to one embodiment of the present invention, a digital hearing device is disclosed. The digital hearing aid includes a microphone for receiving sound, which may include an analog signal. The analog signal is converted by a first converter into a digital signal. Filters are provided to divide the digital signal into multiple signal parts. A signal processor may be provided for each signal part, and performs signal processing on its respective signal part. An adder adds the output of the signal processors, which results in a processed digital signal. A second converter converts the processed digital signal back into an analog signal. A speaker then outputs the analog signal. According to another embodiment of the present invention, a method for enhancing sound is provided.

Abstract: An apparatus (30) and method (80) for predicting electrical property stability of a thin film or conductive substrate (14) prior to multi-probe testing. The present invention utilizes a nanoindenter type device (10) obtaining mechanical properties as a function of displacement depth and applied load into the bond pad surface to accurately predict electrical property stability of the entire substrate or sample under test. In addition, the present invention includes a nanoindenter type device (10) including a second probe (34) having the ability to measure localized electrical properties of the sample while obtaining the mechanical property measurements. This additional electrical measurement is correlated with the mechanical property measurements to accurately predict electrical property stability of the entire conductive substrate, preferably by predicting the presence of an unwanted material surface layer.

Abstract: A process for manufacturing a wafer having a multiplicity of MEMS devices such as mirrors with gimbals formed thereon is disclosed. A silicon wafer having a thickness less than about 300 &mgr;m is attached to a carrier or support wafer by a layer of bonding agent such as a layer or coating of photo-resist. The MEMS devices such as a gimbal mirror are formed on the silicon wafer by providing a mask and etching through the wafer with a DRIE process. Undesired lateral etching at the bottom of the wafer caused by the formation of an electrical charge at the bonding layer is eliminated or substantially reduced by patterning the layer of photo-resist used as the bonding agent such that areas of the support wafer not covered by the bonding layer are aligned with selected etch lines which etch completely through the silicon wafer to form devices.

Abstract: In one aspect of the invention, a method for forming an integrated circuit having an at least substantially doped porous dielectric includes forming a semiconductor device. The semiconductor device includes at least a portion of a semiconductor substrate. The method also includes forming a dielectric layer disposed outwardly from the semiconductor substrate and surrounding at least a portion of the semiconductor device. The dielectric layer includes an at least substantially porous dielectric material doped with at least one dopant. In addition, the method includes forming a contact layer disposed outwardly from the dielectric layer and operable to provide electrical connection to the semiconductor device.

Abstract: A printer controller for processing print data includes a data processor, direct memory access controller, first and second memories with corresponding first and second transfer data busses. A bus switch selectively connects the first and second data transfer busses. When uncoupled, the data processor accessed the said first memory via the first data transfer bus and the direct memory access controller may independently accesses the second memory via the second data transfer bus. When connected, either the data processor or the direct memory access controller may access either memory to the exclusion of the other. This permits better allocation of data transfer bandwidth in the memory controller.

Abstract: A robust, low inductance electronic package for small area semiconductor chips is provided which includes a flexible polymer film having electronic circuitry on one or more major surfaces, a bumped flip chip integrated circuit attached to the first surface, an array of solder balls to the second surface, and the device encapsulated in a plastic molding compound. An assembly and packaging method is disclosed wherein multiple devices are encapsulated simultaneously on a continuous polymer film, thereby providing a method compatible with high volume and low cost manufacturing processes and equipment.

Abstract: A master latch implemented to receive feedback from a slave latch on a different input terminal than a input terminal on which data bits are received. Due to such receiving, the number of transistors/area and/or power consumption requirements (efficiently) may be minimized in implementing a flip-flop. The feedback path may be implemented using a single pass-gate, further enhancing the efficiency of implementation. In addition, clock enable/disable signals may be generated efficiently taking into account an externally received flip-flop disable signal and absence of transitions in the data input bits. When the flip-flop is implemented to support ATPG type sequential scanning testing, a multiplexor may be implemented efficiently to select either the data bits or scan bits.

Abstract: A method for reducing a code size of a software pipelined loop, the software pipelined loop having a kernel and an epilog. The method includes first evaluating a stage of the epilog. This includes selecting a stage of the epilog to evaluate (504) and evaluating an instruction in a reference stage. This includes identifying an instruction in the reference stage that is not present in the selected stage of the epilog (506) and determining if the identified instruction can be speculated (508). If the identified instruction can be speculated, such is noted. If the instruction cannot be speculated, it is determined whether the identified instruction can be predicated (512). If the instruction can be predicated, it is marked as needing predication (514). Next, it is determined if another instruction in the reference stage is not present in the selected stage of the epilog (510). If there is, the instruction evaluation is repeated.

Abstract: A tank-isolated drain extended power device (50, 60, 70, 80) having an added laterally extending heavily doped p-type region (56, 62, 72) in combination with a p-type Dwell (32) which reduces minority carrier buildup. The p-doped regions are defined in a P-epi layer surrounded by a buried NBL region (14) connected with a deep low resistance drain region (16) forming a guardring. This additional laterally extending p-doped region (56,62,72) reduces minority carrier build up such that recovery time is significantly reduced, and power loss is also significantly reduced due to reduced collection time of the minority carriers. The device may be formed as an LDMOS device.

Abstract: An improved bump fabrication process is described that produces a larger diameter/taller solder ball than with a standard mushroom by forming an elongated mushroom having a short axis in the direction of adjacent connection mushrooms and an elongated axis orthogonal to the short axis. The increased larger volume solder when reflowed produces the larger diameter/taller bolder ball bump.

Abstract: An apparatus for providing optical black and offset calibration for an array signal comprising a sequence of voltage levels corresponding to a sequence of voltage samples of charge coupled devices arranged in an array. The apparatus includes a correlated double sampler adapted to receive the array signal and provide as an output a modified array signal comprising a sequence of first corrected output voltage levels. A programmable gain amplifier receives the modified array signal and provides as an output an amplified modified array signal comprising a sequence of second corrected output voltage levels. An analog to digital converter receives the amplified modified array signal and provides as an output a sequence of digital values. A digital signal storage device stores a digital value corresponding to a desired optical black level.

Abstract: Methods are disclosed for fabricating transistor gate structures and high-k dielectric layers therefor by sputter deposition, in which nitridation and/or oxidation or other adverse reaction of the semiconductor material is reduced or minimized by reducing the bombardment of the semiconductor body by positively charged reactive ions such as oxygen ions or nitrogen ions during the sputter deposition process. The sputtering operation may be a two-step process in which ionic bombardment of the semiconductor material is minimized in an initial deposition step to form a first layer portion covering the semiconductor body, and the second step completes the desired high-k dielectric layer. Mitigation of unwanted nitridation and/or oxidation or other adverse reaction is achieved through one, some, or all of high sputtering deposition pressure, repulsive wafer biasing, increased wafer-plasma spacing, low partial pressures for reactant gases, and low sputtering powers or power densities.

Abstract: This invention comprises an architecture for voltage mode control of a voice coil motor in a hard disk drive. In contrast to conventional current mode control, coil current is not sensed or measured, which simplifies the feedback design with less hardware required in the implementation. Common design methodologies for the square root velocity profile, linear velocity profile and regulator/estimator control system designs can be migrated from the current mode architecture to the voltage mode architecture.

Abstract: An image processing system comprising a burst memory; a data processor; and a data buffer coupled between the burst memory and the data processor. The data buffer comprises a block memory (81) coupled to the burst memory and to the data processor via a switch (83); and an access controller (82) coupled to the block memory (81), to the data processor and to the burst memory. The access controller (82) transfers data from the burst memory to the block memory (81) in a format specified to the access controller by the data processor via a first state of the switch (83). The access controller (82) also transfers the formatted data from the block memory (81) to the data processor via a second state of the switch (83). The format can comprise a block of data, a line of data, or data sampled from spatially diverse locations within a picture frame of data.

Abstract: The present invention provides for a method (30) and system (10) for isolating the input nodes (3, 4) and/or the output nodes (5, 8) of an analog device (12) and performing continuity testing thereof without using relays. The system includes an analog device having a pair of input and output terminals and a plurality of resistors (R1-R3 and R4-R6) arranged in parallel and connected thereto. The method for testing continuity of the analog device includes providing a voltage input via at least one of the resistors to either input node, and then measuring the voltage at the same node via a resistor. If a diode drop from ground is sensed there is continuity, and if the applied voltage is sensed at the node there is not continuity. As a result, the invention advantageously isolates the nodes and removes any unwanted capacitance and impedance loading thereon during testing thereof.

Abstract: A semiconductor device and a method of making it involve the semiconductor device (10, 71, 101, 121, 151, 201) having a substrate (11, 73, 153) with spaced source and drain regions (13-14, 76-78, 154). A gate section (21, 81-82, 123, 203) projects upwardly from between an adjacent pair of the regions, into an insulating layer (31, 83, 103, 122, 157). In order to create local interconnects to the source and drain regions through the insulating layer, a patterned etch is carried out using an etch region (36, 87, 126), which extends over one of the gate sections from a location above one of the regions to a location above another of the regions. Etching in this etch region produces recesses (41-42, 91-93, 107-108, 138-139, 158) on opposite sides of and immediately adjacent the gate section. A conductive layer (51, 96, 111, 161, 171) is deposited to fill the recesses, and then is planarized back to the upper ends of the gate sections.

Abstract: A clipping circuit (20) for clipping an input signal to a level corresponding to a regulated power supply voltage (AVDD). The clipping circuit (20) includes a current mirror-like arrangement having a reference transistor (30) and a mirror transistor (32) The input signal (BDATA) is received at the drain of the mirror transistor (32), with the source of the mirror transistor (32) producing the output signal (CLPBDATA). The reference transistor (30) receives a bias current (IBIAS) that is mirrored by the mirror transistor (32) to limit the pull-up drive of the mirror transistor (32) in pulling up the output (CLPBDATA). Disclosed embodiments of the clipping circuit (20; 20′, 20″) include a current source (29) for producing a DC bias current (IBIAS), and a charge pump (34) for producing a transient bias current (IPUMP).

Abstract: A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity, four segments per entry and four valid and dirty bits. When the L2-cache misses, the penalty to access to data within the L3 memory is high. The system supports miss under miss to let a second miss interrupt a segment prefetch being done in response to a first miss. Thus, an interruptible SDRAM to L2-cache prefetch system with miss under miss support is provided. A shared translation look-aside buffer (TLB) is provided for L2 accesses, while a private TLB is associated with each processor. A micro TLB (&mgr;TLB) is associated with each resource that can initiate a memory transfer.