Abstract: A CDM clamp circuit integrated into the interface circuit it is protecting on an integrated circuit. Generally, the integrated CDM clamp circuit and interface circuit are adjacent to each other and share a common device element or component, thus eliminating the need for a metal interconnect. Because there is no interconnect, the parasitic resistance and inductance are also minimized or eliminated from the circuit, thus reducing or eliminating excessive voltage drop. Preferably, the CDM clamp circuit is integrated into the circuit that it is protecting by having the two circuits share the same silicon source region. In a preferred embodiment input circuit, the same diffusion region is the source of both the input transistor and its associated CDM clamp transistor.

Abstract: A symmetric glitch free clock multiplexing circuit allows the input clock to a digital or analog processing unit to be switched from one frequency to the other at any moment during the operation, assuming the respective clocks themselves are stable. There exist no restrictions on the clocks or the switch control signal to be synchronous in any fashion. This circuit guarantees a glitch free output and also prevents short cycling of the output clock. Since all the related clocks and switch control signal are asynchronous, this circuit further eliminates meta-stability problems. Its symmetrical architecture allows the circuit to function with the output clock being switched from slow clock to fast clock and vise versa.

Abstract: A method for detecting synchronization loss of the trellis minimum path metric in V.34 modem communications. The invention detects synchronization loss due to bit inversions in trellis decoding in transmitted digital frames due to a periodic inversion pattern that is used for superframe synchronization. The method provides synchronization loss detection by finding the ratio of moving averages for a series of data blocks to the average of a series of inverted 4D symbols located periodically in the beginning and center of received data frames.

Abstract: A method of producing semiconductor devices including the steps of providing a semiconductor wafer of substantially uniform thickness 22, providing a heat-radiating plate 22, and attaching the heat-radiating plate 20 to the semiconductor wafer. The assembled wafer and heat-radiating plate are diced into individual semiconductor integrated circuits having individual heat radiating plates attached thereto.

Abstract: An embodiment of the invention is a method to reduce the corrosion of copper interconnects 90 by forming a thiol ligand coating 130 on the surface of the copper interconnects 90.

Abstract: A method is described for forming a memory structure using a hardmask (65). The hardmask (65) protects the second polysilicon layer (55) during a SAS etch process. In addition, sidewall structures (95) are formed which protect the inter-polysilicon dielectric layer (45) during the hardmask (65) etch process.

Abstract: An integrated oxide removal and processing system (10) includes a process module (30) that may intentionally add at least one film layer to a single semiconductor wafer (32). The integrated oxide removal and processing system (10) also includes a transfer chamber module (20) used to align the semiconductor wafer (32) for the process module (30). The transfer chamber module (20) may expose the semiconductor wafer (32) to a vaporous solution that is inert with respect to the semiconductor wafer (32) and operable to remove an oxide layer (110) therefrom. More specifically, the semiconductor wafer (32) includes silicon. In a further embodiment, the vaporous solution includes HF. In yet a further embodiment, the vaporous solution includes 0.049% to 49% HF.

Abstract: An information write-register embedded in an integrated circuit (IC) is made of a plurality of independently addressable gate-controlled components formed in an isolated p-well nested in a n-well. Gates over the p-well are positioned on an insulator geometrically formed so that it is susceptible locally to electrical conductivity upon applying an overstress voltage pulse, whereby binary information can be permanently encoded into the write-register. The overstress voltage pulse is applied between the gate and the p-well and is created when a write-enable pulse of predetermined polarity and duration is superposed by a p-well pulse of opposite polarity and shorter duration.

Abstract: The present invention includes a method of forming a semiconductor device.

Abstract: A method for forming an emissive layer for an electroluminescent display is provided that includes positioning a substrate (40) in spaced relation to a port (88) of a microeffusion cell (86). The method then provides for transporting the substrate (40) across the port (88) at a substantially constant rate. The method then provides for effusing an emissive material from the port (88) and adhering at least a portion of the emissive material effused from the port (88) to a defined region of the substrate (40) to form an emissive strip (46) having a substantially constant width on the substrate (40).

Abstract: A screening method in a printer for approximating a gray scale tone with a more limited range image producer using a tree search. An input pixel packed data word is compared with a second data word packed with threshold values. The result of the comparison enables selection of a next second data word with thresholds is a narrower range. This process repeats until a comparison with a second data word having adjacent threshold values. The comparing is preferably performed by subtracting the second data word from the first data word in a splittable arithmetic logic unit and storing respective carry outs from each section. The selection of the next second data word uses the stored carry outs from each section. The next second data word can be determined by extracting a left most one of the stored carry outs for use as an index into a table. Alternatively, the stored carry outs can be used directly as an index into a table. An output pixel value is determined for each pixel.

Abstract: A hand-held device comprising a housing (10) shaped and dimensioned to allow the device to be hand held, a display (12) secured to the housing for displaying moving pictures on a frame-by-frame basis, and a camera (16, 18) having an optical axis (O) extending generally away from the display to image a person who is viewing the display. The hand-held device further comprises a sensor (20) configured to determine a rotational angle between an alignment axis (V) of the hand-held device and a reference alignment axis in real space. Alternative embodiments use a reference alignment axis obtained on the basis of data content of the images, as determined by image processing techniques. In this way, subjective picture quality can be improved by compensating for vertical mis-alignment of the image content of the frames obtained by the camera.

Abstract: An embodiment of the invention is a metal layer 14 of a back-end module 6 where the height of the interconnects 17 is greater than the height of the dielectric regions 20. Another embodiment of the invention is a method of fabricating a semiconductor wafer 4 where the height of the interconnects 17 is greater than the height of the dielectric regions 20.

Abstract: An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% O2); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C.

Abstract: A flip flop (30) comprising a master stage (34) comprising a first plurality of transistors (54, 56), wherein each of the first plurality of transistors comprises a selective conductive path between a source and drain. The flip flop also comprises a slave stage (42) comprising a second plurality of transistors (60, 62, 64, 66), wherein each of the second plurality of transistors comprises a selective conductive path between a source and drain. For the flip flop, in a low power mode the flip flop is operable to receive a first voltage (VDD) coupled to the selective conductive path for each of the first plurality of transistors. Also in the low power mode, the flip flop is operable to receive a second voltage (VDDL) coupled to the selective conductive path for each of the second plurality of transistors. Lastly, the second voltage is greater than the first voltage in the low power mode.

Abstract: An MOS transistor in the surface of a semiconductor substrate (180) of a first conductivity type, which has a grid of isolations (171) in the surface, each grid unit surrounding a rectangular substrate island (102). Each island contains two parallel regions of the opposite conductivity type: one region (174) is operable as the transistor drain and the other region (173) is operable as the transistor drain, each region abutting the isolation. A transistor gate (105) is between the parallel regions, completing the formation of a transistor. Electrical contacts (106) are placed on the source region (173) so that the spacing (120) between each contact and the adjacent isolation is at least twice as large as the spacing (121) between each contact and the gate. A plurality of these islands are interconnected to form a multi-finger MOS transistor.

Abstract: A digital system and method of operation is provided in which several processing resources (340) and processors (350) are connected to a shared translation lookaside buffer (TLB) (300, 310(n)) of a memory management unit (MMU) and thereby access memory and devices. These resources can be instruction processors, coprocessors, DMA devices, etc. Each entry location in the TLB is filled during the normal course of action by a set of translated address entries (308, 309) along with qualifier fields (301, 302, 303) that are incorporated with each entry. Operations can be performed on the TLB that are qualified by the various qualifier fields. A command (360) is sent by an MMU manager to the control circuitry of the TLB (320) during the course of operation. Commands are sent as needed to flush (invalidate), lock or unlock selected entries within the TLB. Each entry in the TLB is accessed (362, 368) and the qualifier field specified by the operation command is evaluated (364).

Abstract: A polysilicon layer of a gate structure is covered by an implant blocking layer (e.g., silicon nitride). The implant blocking layer blocks introduction of implanted dopants while implanting an initial dose of first conductivity type dopant (e.g., for drain extension regions). The implant blocking layer is then removed and an additional dose of first conductivity type dopant in implanted to form the main source/drain regions. Then, metal is deposited and reacted to form a conductive silicide.

Abstract: A method for previewing an image in a camera prior to output. The method includes steps of gathering image data, storing the image data, calculating display parameters using the stored image data, storing the display parameters in a look-up table; and applying the display parameters in the look-up table to at least a portion of the image data to produce preview image data. The display parameters can be quickly calculated using a digital signal processor to achieve real-time image previewing. The parameters used in an embodiment camera are vertical down sampling (51) white balance and gain control (52), horizontal up/down sampling (53), and color space conversion and gamma correction (55). The resulting preview processed image may be stored in memory via an interface (56) and viewed via a preview display.

Abstract: A method of CMP polishing of a semiconductor wafer is described that includes using a polishing pad on a platen/table with the polishing pad including a sub-pad containing pockets of magnetorheological fluid. The stiffness of the sub-pad is controlled by selectively applying a magnetic field at selective pockets containing magnetorheological fluid to change the viscosity of the magnetorheological fluid. The changing stiffness increases the polishing rate of the pad in the areas of the magnetic field.