Abstract: A method of forming a semiconductor circuit (20). The method forms a first transistor (NT1) using various steps, such as by forming a first source/drain region (361) as a first doped region in a fixed relationship to a semiconductor substrate (22) and forming a second source/drain region (362) as a second doped region in a fixed relationship to the semiconductor substrate. The second doped region and the first doped region are of a same conductivity type. Additionally, the first transistor is formed by forming a first gate (283) in a fixed relationship to the first source/drain region and the second drain region. The method also forms a second transistor (ST1) using various steps, such as by forming a third source/drain region (341) as a third doped region in a fixed relationship to the semiconductor substrate and forming a fourth source/drain region (342) as a fourth doped region in a fixed relationship to the semiconductor substrate.

Abstract: This invention comprises a multiple transaction advanced high performance bus AHB system using two separate fully autonomous AHB buses, each having its own bus arbitration system with decoding to allow for simultaneous activity on the two AHB buses. The two buses are separated by and synchronized with an AHB-to-HTB bus bridge. The first bus, the Memory Bus AHB, contains the CPU and DMA as bus masters and the external memory controller and internal memory as slaves. The second bus, the Data Transfer Bus HTB, contains the high performance peripheral and any local RAM required.

Abstract: A method for optical digital signal processing, comprises configuring a plurality of binary mirrors to allow a subset of the binary mirrors to represent a range of values. The plurality of binary mirrors comprise a digital micromirror device. Light from a light source is received at the digital micromirror device. The intensity of the light is altered to represent one of the values based, at least in part, on the configuration of the subset of the binary mirrors. The altered light is transmitted from the digital micromirror device to a detector array.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a TiAlON bottom electrode diffusion barrier layer prior to formation of the bottom electrode layer in an FeRAM capacitor stack. Subsequently, when performing the capacitor stack etch, the portion of the TiAlON diffusion barrier layer not covered by the FeRAM capacitor stack is etched substantially anisotropically due to the oxygen within the TiAlON diffusion barrier layer substantially preventing a lateral etching thereof. In the above manner, an undercut of the TiAlON diffusion barrier layer under the FeRAM capacitor stack is prevented. In another aspect of the invention, a method of forming an FeRAM capacitor comprises forming a multi-layer bottom electrode diffusion barrier layer. Such formation comprises forming a TiN layer over the interlayer dielectric layer and the conductive contact and forming a diffusion barrier layer thereover.

Abstract: A method and apparatus is provided for operating a digital system having several processors (102, 104) and peripheral devices (106, 116) connected to a shared memory subsystem (112). Two or more of the processors execute separate operating systems. In order to control access to shared resources, a set of address space regions within an address space of the memory subsystem is defined within system protection map (SPM) (150). Resource access rights are assigned to at least a portion of the set of regions to indicate which initiator resource is allowed to access each region. Using the address provided with the access request, the region being accessed by a memory access request is identified by the SPM. During each access request, the SPM identifies the source of the request using a resource identification value (R-ID) provided with each access request and then a determination is made of whether the resource accessing the identified region has access rights for the identified region.

Abstract: This invention presents a unique implementation of the extrinsic block the turbo decoder that solves the problem of generation and use of precision extension and normalization in the alpha and beta metrics blocks. Both alpha metric inputs and beta metric inputs are processed via a circle boundary detector indicating the quadrant of the two's complement input and a precision extend block receiving an input and a corresponding circle boundary input. An extrinsics block includes a two's complement adder of the precision extended alpha and beta metrics inputs. The proposed solution obviates the need for normalization in the alpha and beta metric blocks.

Abstract: A first dielectric layer (30) and a second dielectric layer (40) are formed over an etch stop layer (20). A hardmask layer (50) is formed over the second dielectric layer and a via (62) is formed in the first dielectric layer (30) and the second dielectric layer (40). A trench (85) is formed mostly in the second dielectric layer (40) by fully or partially removing BARC from the via (62) are partially etching the trench (85) and prior to completion of the trench etch process.

Abstract: An integrated circuit structure (8) includes a plurality of solid state electronic devices and a plurality of conductive elements (12, 14) that electrically couple the electronic devices. The integrated circuit structure (8) also includes a dielectric layer (16) positioned between two or more of the conductive elements (12, 14). A liner (18) is positioned between at least a portion of the dielectric layer (16) and a conductive element (12, 14). The liner (18) is formed from a compound that includes silicon and either carbon and nitrogen.

Abstract: A data exchange system that exchanges data between processors is provided. The system includes a host processor and a target processor. Data is exchanged by forming a data pipeline between the target processor and the host processor. The data pipeline includes a data unit on the target processor, an emulator and a device driver on the host processor. The data exchange system sends data through the data pipe line by transferring the data from a target memory on the target processor with the data unit to the emulator. The data exchange system transfers the data from the emulator to the first device driver.

Abstract: A supply reference voltage circuit is coupled to an output node, a supply voltage node and a supply reference voltage node and is operable to connect the output node to the supply reference voltage node and prevent current flow through an output device coupled to the output node in response to sensing a low voltage level at the supply voltage node and a non-zero voltage at the output node. The circuit is further operable to connect the supply reference voltage node to the supply voltage node in response to the voltage at the output node being a threshold voltage above the voltage at the supply voltage node. The circuit is further operable to bypass a blocking diode in response to sensing a high voltage level at the supply voltage node.

Abstract: A secure computing system stores a program, preferably the real time operating system, that is encrypted with a private key. A boot ROM on the same integrated circuit as the data processor and inaccessible from outside includes an initialization program and a public key corresponding to the private key. On initialization the boot ROM decrypts at least a verification portion of the program. This enables verification or non-verification of the security of the program. The boot ROM may store additional public keys for verification of application programs following verification of the real time operating system. Alternatively, these additional public keys may be stored in the nonvolatile memory. On verification of the security of the program, normal operation is enabled. On non-verification, system could be disabled, or that application program could be disabled. The system could notify the system vendor of the security violation using the modem of the secure computing system.

Abstract: A repair fuse element and method of construction are disclosed that eliminate or substantially reduce the disadvantages and problems associated with prior fuse elements. In one embodiment, the fuse element is constructed with a rectangular-shaped contact. The contact is made long enough so that it makes contact at each end with a metal layer, but design rule spacing is still maintained between the connections with the metal layer. The overlapping areas between the rectangular contact and the metal layers are asymmetrical. Alternatively, these overlapping areas are smaller than the design rule overlap requirements. In a second embodiment, a fuse element is constructed with a plurality of rectangular-shaped contacts. As a result, a current value that is significantly lower than conventional fuse current values, can be used to melt such a contact or blow the fuse.

Abstract: A symbol detector provides a delay-less estimate of a transmitted symbol. The symbol detector includes a symbol input for receiving a sequence of input symbols, a plurality of accumulators (ACC) for storing trellis state costs, a plurality of adders (202) for summing the square of distances between an input symbol and a constellation symbol for a trellis branch with the trellis state costs, and a plurality of comparators (203) connected to the adders for determining minimum costs and providing those costs to the accumulators. A memory (201) is connected to an associated comparator for storing the minimum cost determined the associated comparator. A minimization unit (204) outputs an index value of comparators with the lowest value, and a branch table unit (205) outputs a delay-less estimate of a transmitted symbol based on the index of the trellis branch with lowest cost that enters the trellis state with lowest cost and an input symbol.

Abstract: A semiconductor device (200) that includes a semiconductor substrate (210), semiconductor features (230, 235, 240, 260) located thereover and an insulating photoconductive layer (270) coupling the semiconductor features (230, 235, 240, 260). The photoconductive layer (270) is configured to provide conductivity between the semiconductor features (230, 235, 240, 260) in a presence of a plasma.

Abstract: A graphing calculator (10) or other computer based teaching tool that displays inequalities on a display screen. In contrast to prior art devices, the present invention provides displays of inequalities that are mathematically correct and consistent with non-electronic display of inequalities such as textbooks and black board representations to reinforce traditional teaching methods and help the student or user to readily see and understand the mathematical concepts involved. The display methods of the present invention are particularly useful for small, low-resolution displays that are typical of handheld computers and calculators.

Abstract: A method for reducing a leakage current in an integrated circuit is provided that includes controlling one or more inputs of an integrated circuit such that one or more logic elements within the integrated circuit are set to one or more selected values. The selected values produce a minimum leakage current associated with the integrated circuit when the integrated circuit is operating in a standby mode.

Abstract: A portable particle detection and removal system (100) that connects to a house vacuum (200). A particle sensor (106) is connected between two hoses: one (102) connected to the house vacuum (200) and one (104) for vacuuming the wafer equipment chamber. A smaller diameter hose (104) may be used for vacuuming the wafer equipment chamber. The particle sensor detects (106) incoming particles and a particle count is displayed for the operator. A modulated cleaning system (112) modulates the vacuum pressure in the second hose (104) between two vacuum pressure states.

Abstract: The present invention provides a solution for interleaving data frames, in a digital subscriber line system in which the data frames are divided into first and second codewords such that the first codeword comprises an even number of data bytes and the second codeword comprises an odd number of data bytes. With an interleaver depth (D) greater than a number of data bytes in the codewords (N), the codewords are written to a first matrix (51) in a predetermined manner (220), and read from the first matrix (51) in a predetermined manner (240 or 250) in which the data bytes of the codewords are delayed by a number of bytes. The codeword data bytes (defined by: B0, B1, . . . , BN−1) are delayed by an amount that varies linearly with a byte index, where byte Bi (with index i) is delayed by (D−1)×i bytes. Further, de-interleaving the interleaved data frames can be implemented by a reverse interleaving writing (340 or 350) and reading (320) in a second matrix (52).

Abstract: A controller that supports both aligned and unaligned PIO data transfers associated with ATAPI devices in a fashion that reduces command overhead to improve ATAPI device system performance. A 32-bit wide sector FIFO, implemented with a 32-bit single port RAM using read and write pointer control logic, is used to store packet data transmitted to and received from the other data bus (i.e. USB). The 32-bit single port RAM functions as a FIFO to allow both the USB side and the ATAPI side to simultaneously access the sector FIFO.

Abstract: An array (90) of transistors (50) formed in a p-type layer (34), and including a second heavily doped p-type region (56) laterally extending proximate the drain of each transistor to collect minority carriers of the transistors. A deep n-type region (16) is formed in the p-type layer (34) and proximate a n-type buried layer (14) together forming a guardring about the drain regions of the plurality of transistors. The array of transistors may be interconnected in parallel to form a large power FET, whereby the heavily doped second p-type region (56) reduces the minority carrier lifetime proximate the drains of the transistors. The guardring (14, 16) collects the minority carriers (T1) and is isolated from the drains of the transistors. Preferably, the transistors are formed in a P-epi tank that is isolated by the guardring. The P-epi tank is preferably formed upon a buried NBL layer, and the deep n-type region is an N+ well extending to the buried NBL layer.