Abstract: An amplifier includes a differential amplifier (10) having an input stage (20) for amplifying a differential input signal (Vin), and an output stage (6) coupled to the input stage (20) for producing and output signal (Vout). The input stage (20) includes main input circuitry (20A) for amplifying small-signal values of the input signal (Vin) and alternative input circuitry (20B) for amplifying the input signal (Vin) during conditions which cause thermal imbalance in the main input circuitry (20B). The input stage (20) includes switching circuitry (12) for coupling the input signal (Vin) to the main input circuitry (20A) during normal small-signal operating conditions and to the alternative input circuitry (20A) during large-signal operating conditions that cause thermal imbalance in the main input circuitry (20B).

Abstract: A wireless communication system (10). The system comprises a user station (12). The user station comprises despreading circuitry (22) for receiving and despreading a plurality of slots received from at least a first transmit antenna (A121) and a second transmit antenna (A122) at a transmitting station (14). Each of the plurality of slots comprises a first channel (DPCH) comprising a first set of pilot symbols and a second channel (PCCPCH) comprising a second set of pilot symbols. The user station further comprises circuitry (50) for measuring a first channel measurement (&agr;1,n) for each given slot in the plurality of slots from the first transmit antenna and in response to the first set of pilot symbols in the given slot. The user station further comprises circuitry (50) for measuring a second channel measurement (&agr;2,n) for each given slot in the plurality of slots from the second transmit antenna and in response to the first set of pilot symbols in the given slot.

Abstract: An apparatus for and method of generating a clock signal having a desired frequency that is derived from a clock source having any arbitrary,frequency. The mechanism of the present invention generates an average rate, very close to the optimal rate desired, by ‘swallowing’ or absorbing clock cycles of the available frequency source. Precise timing is achieved by adding correcting time intervals, which are based on counting pulses from the higher rate clock source. The clock frequency generator comprises a standby mode state machine and a jitter calculation processor. Timing calculations are performed by the jitter calculation processor and the standby mode state machine functions to generate the desired standby mode clock frequency. The state machine utilizes counters to track the number of cycles of the available clock and the number of generated cycles of the standby clock.

Abstract: A novel and useful mechanism for measuring the time duration between asynchronous events. The mechanism utilizes two metastability resolvers, one for detecting the rising edge of the input signal and one for detecting its falling edge. The input signal is typically assumed to have some known nominal clock rate, but its exact frequency and phase (timing of transitions) are not known. Each of the two metastability resolvers comprises two branches of cascaded flip flops, each clocked off the rising edge and falling edge of a fast clock. Each metastability resolver functions to output an edge event signal and a clock phase signal indicating which edge of the fast clock the rising (or falling) edge of the data signal was closer to. The edge event signals are used to start and stop a counter clocked off the fast clock. The clock phase is used to correct (i.e. compensate) the counter value depending on which half cycle of the fast clock the rising and falling edge of the data signal arrived in.

Abstract: Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.

Abstract: A PC card and corresponding WLAN system having an improved DAC operable at higher speed than heretofore achievable which exploits the sigma-delta principle in a different way. More particularly, the invention comprises a PC card (302) and corresponding WLAN system (300) that implement a digital-to-analog conversion circuit (105) including a storage means (110), such as a read only memory, for storing delta-sigma analog sequences corresponding to all possible values of a digital input (106) coupled to a plurality of one-bit digital to analog converters (120, 122, 124, 126). Each of the digital-to-analog converters (120, 122, 124, 126) are clocked by multi-phase clocks, such that each phase applied to each one of the digital-to-analog converters (120, 122, 124, 126) is delayed with respect to one another by the oversampling period.

Abstract: A group of client calculators (18) communicates by determining whether a aster calculator (14) is a member of the group. If the master calculator (14) is present, the client calculators (18) determine whether the master calculator (14) has allowed communication between the client calculators (14). The client calculators may communicate if the master calculator (14) is not present or if the master calculator (14) is present and has allowed communications between other of the client calculators (18).

Abstract: Startup operation of a DC/DC switching regulator is controlled by providing a first signal (MAXDC) whose waveform has a duty cycle that varies over time, providing a second signal (620, 622) indicative of a load condition of the regulator, and combining the first and second signals to produce a third signal (312, 311). The third signal is used to control a power switch (231, 324) of the regulator.

Abstract: Methods and apparatus are disclosed for reducing output ripple voltages in bandgap voltage reference circuits. Ripple rejection circuitry is connected to a supply voltage and a first control signal, such as from an amplifier. The ripple rejection circuitry provides a second control signal representative of a difference between the supply voltage and the first control signal. The second control signal is then used to generate a reference voltage output. The incorporation of the supply voltage component in the second control signal operates to reduce or suppress the effects of power supply ripple on the bandgap voltage output.

Abstract: A semiconductor device comprising a lead frame that includes a large area mount pad having small elevated pads to which a semiconductor chip is attached. The small mount pads coupled with usage of a minimal amount of chip attach adhesive provide improved reliability against vapor phase package cracking, and further allow a given lead frame to be used by a family of chip sizes and shapes. The large pad provides good thermal dissipation, as well as stress relief during fabrication of the lead frame.

Abstract: A method of transferring electronic equivalents (32) of published items (18) is provided wherein bar codes (116, 118) are attached on the items (18) prior to distribution to subscribers (12). The bar codes (116, 118) are scanned by a bar code reader (22), formatted into a predetermined message format compatible with network protocols and transmitted to the associated publishing authority (30). Based on the bar code information, the publisher (30) will either push the requested electronic equivalent (32) or transfer a pointer to the user (12) to a network cite containing the requested electronic equivalent (32). Alternatively, the publisher (30) can push updates of published items (32) to users (12).

Abstract: A mobile communication system is designed with an input circuit coupled to receive a first plurality of signals (rj(i+&tgr;j), i=0−N−1) during a first time (T0-T1) from an external source and coupled to receive a second plurality of signals (rj(i+&tgr;j), i=N−2N−1) during a second time (T1-T2) from the external source. The input circuit receives each of the first and second plurality of signals along respective first and second paths (j). The input circuit produces a first input signal (Rj1) and a second input signal (Rj2) from the respective first and second plurality of signals. A correction circuit is coupled to receive a first estimate signal (&agr;j1), a second estimate signal (&agr;j2) and the first and second input signals. The correction circuit produces a first symbol estimate (S1) in response to the first and second estimate signals and the first and second input signals.

Abstract: A concentrator (11) coupled to a wired network (13) also acts as a master device relative to each of a plurality of ad hoc wireless communication networks (15), thereby permitting wireless communication devices in the ad hoc networks to access the wired network. The concentrator utilizes antenna array processing and beamforming techniques when communicating with the devices of the various networks, in order to advantageously reduce communication interference between the networks.

Abstract: The described embodiments of the present invention provide a computer docking station having connection means for coupling to an external monitor and an external keyboard, means for connecting the portable computer to the docking station, and at least one PCMCIA option card slot in the docking station. In a preferred embodiment, the computer docking station further includes a controller in the docking station to provide the necessary hardware interface between the PCMCIA cart slot and the portable computer and software means for providing the necessary driver support.

Abstract: A computer uses an environmental manager (20) to detect and respond to changing environmental conditions, in order to enhance and simplify a users interaction with the computer. Environment changes are detected by a plurality of informants (22), each of which has a specified function. Informants communicate through a CIM (26). The CIM (26) establishes communication channels with each informant regarding which information will be provided by the informant and which information that informant needs from other informants. Informants (22) may receive environmental information from a number of sources, including physical location detectors, hardware configurations, software configurations, and network connections. As environmental conditions change, the informants and applications may respond to the changes. A particular capability to respond is the autolaunch capability which detects user behavior and uses this knowledge to automatically load a program responsive to changing environmental conditions.

Abstract: A shape modulation transmit loop with digital frequency control permits spectral shaping of a digital pulse stream (12) by controlling the slew rate of the transition signal (16) between successive pulses. The loop is formed when the digital data stream is fed into an up/down counter (152) whose output is coupled to a programmable memory means (154), such as RAM, EEPROM, flash memory or similar electronic storage means. The output (108) of the programmable memory (154) forms a first input to an adder (112) which drives an accumulator (52) with specified steps. Values corresponding to the desired waveform (70) are stored in a lookup table (60) which is coupled to a digital-to-analog conversion circuit (64) which uses the values in the lookup table (60) to construct a sine wave output signal (70) corresponding to the frequency set by the current specified step of the up/down counter (152).

Abstract: A new family of current mode logic (CML) gates (14) which, in one embodiment includes OR/NOR and AND/NAND gates, as well as more complex logic functions. The circuit uses a complementary signal to drive the gate of a feedback transistor (19) which has the effect of pseudo differential operation. Although it uses only single-ended inputs (A, B), because of this feedback aspect, the circuit has many of the advantages of a differential circuit such as low-voltage operation, higher immunity to noise, and less sensitivity to parasitic elements.

Abstract: A system for wireless communication between a base station 30 and one or more remote stations 32 and 34 wherein a desired signal has associated therewith an identifier tone (a SAT in the vernacular of the AMPS system) and wherein interfering signals may have associated therewith identifier tones at different frequencies. A superresolution technique is used in the system to process the received data and to determine the relative magnitudes of any identifier tones which may be present in the received data. In the disclosed embodiment, the superresolution technique utilized is a least square error process. The resulting estimates are used by the system to facilitate the communication function.

Abstract: A digitally-controlled oscillator (DCO) (60), such as may be used in clock generator or clock recovery circuitry in an integrated circuit, is disclosed. The disclosed DCO (60) is a single-stage oscillator including a variable load implemented as a binary-weighted array of switched capacitors (40). Each of capacitors (40) has a plate connected to a common node (X), and a plate that receives a signal corresponding to one bit of a digital control word (DCOCW). The common capacitor node (X) is also connected to the input of a Schmitt trigger (42) that produces the output clock signal (OUTCLK) and a feedback signal that is applied to logic (38, 39) that inverts the common node of the capacitors (40). The switching time at the input of Schmitt trigger (42) depends upon the variable load presented by the array of switched capacitors (40), which is controlled by the digital control word (DCOCW). As a result, the clock signal (OUTCLK) is digitally synthesized by a single stage of the DCO (60).

Abstract: A system for wireless communication between a base station 30 and one or more remote stations 32 and 34 wherein the beam pattern of the receiving antenna 50-52 can be adaptively formed to track a desired signal. A series of weights is applied, one to each output of the elements of the receiving antenna and the weighted output summed to form the antenna output. The weights are adaptively modified so as to focus the beam in the direction of one of many signals which may be present in the data received by the antenna. A least-square-error process is used to identify if the signal beamed on is the desired signal. If such is not the case, the weights are modified to null out the earlier signal and to focus the pattern on another signal.