Abstract: The present invention discloses a PLL (90), which may be implemented in software, hardware, or a combination of software and hardware, which comprises a sync detector (92) adapted to output a phase error (152), a vertical sync discrete time oscillator (DTO) block (98) adapted to output a vertical sync DTO (130) based on the phase error (152), and an output logic (100) adapted to detect a vertical sync based on the vertical sync DTO (130).

Abstract: An operational amplifier includes an input stage for producing a voltage signal in response to an input signal. An output stage includes an output transistor having a source coupled to a supply voltage and a gate coupled to receive the voltage signal. An output cascode transistor has a source coupled to a drain of the output transistor and a drain coupled to an output conductor. A gate control amplifier includes an input stage including a first input transistor having a control electrode coupled to the source of the output cascode transistor and an active load transistor, the input transistor and the active load transistor being coupled to a gate of the output cascode transistor. The gate control amplifier also includes a feedback amplifier having an input coupled to the source of the output cascode transistor and an output coupled to a control electrode of the active load transistor.

Abstract: Systems and methods are provided for providing a filtered, thermometer coded output signal from an N bit digital input, where N is an integer greater than one. A truncated lookup table provides a corresponding truncated thermometer code in response an address related to the N bit digital input. A code recovery assembly transforms the truncated thermometer code into a thermometer coded output according to a recovery bit associated with the N bit digital input.

Abstract: An apparatus for indicating detection of an onset of a high-voltage condition at an output locus of a signal converter device, the signal converter device including a switching network for switchingly controlling a potential at a circuit node coupled with the output locus in response to a control signal received from a control signal source, includes: (a) a first sensing unit coupled for sensing a parameter at the circuit node; (b) a second sensing unit coupled for sensing the control signal; and (c) a comparing device coupled with the first sensing unit and with the second sensing unit; the comparing device effecting comparison of a first signal from the first sensing unit with a second signal from the second sensing unit. The comparing device effects the detection when the first and second signals have a predetermined relationship, then the apparatus effects the indicating.

Abstract: An asynchronous sample rate converter interpolates and filters a digital audio input signal to produce a filtered, up-sampled first signal. A FIFO memory receives the first signal and stores samples thereof at locations determined by a write address and presents stored samples from locations determined by a read address. The presented samples are passed through an interpolation and resampling circuit to produce a continuous-time signal which is re-sampled to produce a signal that is up-sampled relative to a desired output. That signal then is filtered and down-sampled to produce the output signal. Sample rate estimating circuitry computes a difference signal representative of a time at which a data sample of the audio input signal is received and a time at which a corresponding audio output sample is required, and address generation circuitry generates the read and write addresses.

Abstract: A switch mode power converter is provided which includes a switching cell with a supply input, an output and a control input. A summing comparator has first and second differential input pairs and an output. The output is connected to the control input of the switching cell. An oscillator provides a periodic waveform that is applied to a first one of the inputs of the first differential input pair of the summing comparator. An adjustable reference voltage source provides an adjustable reference voltage a predetermined fraction of which is applied to a second one of the inputs of the first differential input pair of the summing comparator. An error amplifier has differential outputs coupled to the second pair of differential inputs of the summing comparator and a differential input pair.

Abstract: A low noise AC coupled amplifier having transistors sharing bias currents, and having a low band-pass corner frequency and consuming low power. The amplifier may be used in a magneto-resistive (MR) preamplifier to amplify a response from a MR sensor. Bipolar and MOS transistors are used in the front end, utilizing the advantages of each transistor type to achieve low noise as well as low band-pass corner. The amplifier has a modified structure achieving lower power by using a PNP transistor instead of an NPN transistor.

Abstract: An apparatus for effecting signal chopping in an amplifier device having an amplifier section, a modulation section, a ramp generating section and a clock section includes: at least one signal treating unit coupled among the clock section, the amplifier section and the ramp generating section. The at least one signal treating unit cooperates with the clock section to effect providing a chopping signal to the amplifying unit at a chopping frequency and to effect providing a ramping signal at a ramping frequency to the ramp generating section. The chopping frequency is neither a fundamental frequency nor a harmonic frequency of the ramping frequency.

Abstract: A multi-module DC-DC converter provides synchronization between modules based on identification of a module within a chain. A resistor network can be used for the chain so that each module obtains a particular voltage based on its position within the chain. A master module provides a source current to drive the chain so that each module can determine its relative position in the chain based on voltage readings. With this configuration, a master module can determine how many modules are in the chain, and each slave module can determine its relative position in the chain. The module information contributes to synchronization between the modules for use in current ripple cancellation, for example, in the multi-module DC-DC converter.

Abstract: A CMOS LC-tank oscillator includes a pair of symmetric inductors and a differential pair of transistors. The inductors have a first one of their terminals interconnected at a supply node to which a voltage supply is applied through a supply resistor and a second terminal connected to the drain of a respective one of the transistors. The transistors have their sources interconnected at a tail node which is connected to ground through a tail resistor. A current control loop controls a core current between the supply and tail nodes so as to keep a voltage drop across the tail resistor at a level determined by a reference voltage. The current control loop keeps the core current between the supply and tail nodes at the required level so that a resistor may replace the upstream supply voltage regulator and another resistor may replace the downstream bias regulator. Consequently, sources of noise injected into the LC-tank type oscillator are eliminated.

Abstract: The present invention provides a current-sense bias circuit for use with a magnetoresistive head. In one embodiment, the current-sense bias circuit includes a voltage biasing portion configured to provide a bias voltage across the magnetoresistive head thereby establishing a bias current through the magnetoresistive head. Additionally, the current-sense bias circuit also includes a current sensing portion coupled to the voltage biasing portion and configured to sense a change in the bias current based on a resistivity change of the magnetoresistive head.

Abstract: A method and circuit for eliminating input voltage offset in an amplifier circuit are provided. An exemplary offset correction circuit is configured with DC restoration to eliminate the DC input voltage offset by suitably providing a correction voltage to correct an input voltage offset during operation of the amplifier circuit, without realizing recovery time problems associated with AC coupling. An exemplary offset correction circuit is configured with DC restoration and comprises a timing circuit, a sample and hold circuit, and a feedback circuit to provide a correction voltage signal to correct input voltage offset. The timing circuit is configured to determine a “dead time” and “live time” for operation of the amplifier circuit. During the “dead time” period the sample and hold circuit will sample a differential signal across the DC coupling and provide a feedback signal through feedback circuit to correct input offset voltage.

Abstract: An apparatus is for detecting body diode conduction in a semiconductor device that includes first regions fixed with a substrate having an upper surface to establish a source, gate and drain with drain-to-source current flow parallel with the surface. The first regions experience body diode conduction in a first inter-region current flow among first involved regions. The apparatus includes: second regions fixed with the substrate and substantially similar in relative size and placement with respect to other second regions as a corresponding first region is in relative size and placement with respect to other first regions. The second regions experience model body diode conduction in a second inter-region current flow among second involved regions. The model body diode conduction occurs generally contemporaneously with the body diode conduction. Selected second regions are coupled with selected first regions to establish a connection locus to permit detecting the model body diode conduction.

Abstract: A circuit (90) and method are presented to accurately determine a BEMF voltage of a VCM coil (20) after termination of a driving current in a first current direction in the coil (20). The circuit includes a circuit for activating selected VCM coil driver transistors (44–47) to apply a current to the coil (20) in a direction opposite the first current direction to generate a magnetic field to oppose eddy currents established in structures adjacent the coil (20) by the driving current. The time that the eddy current opposing current may be applied may be determined, for example, by determining a magnitude of the original current command, a time that the coil spends in flyback, or a magnitude of the original driving current, and adjusting the time of application of the eddy current opposing current accordingly.

Abstract: An apparatus for applying write signals including a first write signal and a second write signal to write information to a memory device includes a current directing circuit receiving the write signals and directing a write current to establish a write voltage between first and second write loci in a first or second excursion toward a first or second polarity in response to the first or second write signal. The first and second write loci are coupled with supply locus via an adjacent first or second impedance unit and a first or second switching unit. The first and second switching units are controlled at first and second control loci by the first and second write signals. First and second boost systems are coupled with the first and second control loci for boosting the write voltage toward the first and second polarities during first and second excursions.

Abstract: A system and method of dynamic offset compensation that is particularly adaptable to analog-to-digital conversion performed in control applications employing highly integrated Digital Signal Processor (DSP) devices. The system providing dynamic compensation of Analog-to-Digital Converter (ADC) zero level offset errors includes an integrated DSP device with a multi-bit ADC and a PWM waveform generator for producing at least one PWM output, and an external low pass filter. The ADC receives an analog input signal and converts it into a corresponding digital output signal. The DSP device measures the zero level offset of the ADC output signal, and dynamically controls characteristics of the PWM output based on the measured offset. The low pass filter receives the PWM output and applies a corresponding controlled DC output voltage to the low reference voltage input of the ADC to dynamically compensate for the zero level offset error.

Abstract: An amplifier circuit includes first (7A) and second (7B) operational amplifiers connected in a parallel configuration. A first terminal (12) of a first input resistor (5) is coupled to one input of both of the first (7A) and second (7B) amplifiers. A first terminal (15) of a second input resistor (6) is coupled to another input of both of the first (7A) and second (7B) amplifiers. A differential input voltage is applied between the second terminals of the first and second input resistors. The output signals of the first (7A) and second (7B) operational amplifiers are combined to produce an output signal (11AB) representative of feedback currents produced in the first (5) and second (6) input resistors. Upper and lower common mode input voltage ranges associated with the differential input voltage extend substantially above and below the upper and lower supply voltages, respectively, of the amplifier circuit.

Abstract: An apparatus for generating pulses includes: (a) A delay unit having an input delay locus for receiving a delay unit input signal and an output delay locus for presenting an output delay signal. The delay unit output signal is delayed by a delay interval with respect to the input delay signal. (B) A latch coupled with the delay unit to selectively keep the delay unit input signal at at least one predetermined signal level.

Abstract: A simplified comparator circuit (10) having hysteresis and lower power requirements for its implementation. The circuit (10) includes 2 minimum-sized MOSFETs (MN4, MN5) providing feedback from the circuit output to an input device (MN1) body to produce hystereis, requiring very little power. This invention is suitable for applications not requiring a precisely set hysteresis magnitude.

Abstract: A power supply has a plurality of switching regulators providing a like plurality of regulated output voltages. The oscillators of the switching regulators are synchronized with one another by a synchronization signal. A synchronization signal detector is provided on one or more of the switching regulators to shift the switching frequency of the oscillator to a lower frequency upon detection of a synchronization signal.