Abstract: An ESD protection structure which includes, preferably a single semiconductor chip, a forward SCR for coupling across a source of potential and a reverse SCR for coupling across the same source of potential which is non-symmetrical to the forward SCR. The breakdown voltage of the forward SCR is different from the breakdown voltage of the reverse SCR. Each of the SCRs has a separate triggering mechanism. None of the anode, cathode and triggering elements of the forward SCR are common to the reverse SCR. A unidirectional device, preferably a Schottky diode, is disposed in the body of semiconductor material between the forward and reverse SCRs to prevent conduction from the body of semiconductor material when the source of potential across the SCRs is reversed.

Abstract: The charge coupled device (CCD) charge detection system includes a first CCD register having N non-destructive charge readouts where N is an integer greater than one, and N second CCD registers coupled to the N non-destructive charge readouts where each of the N second CCD registers is coupled to a corresponding one of the N non-destructive charge readouts.

Abstract: A rotary union (20) is disclosed for allowing fluid to flow between a first environment and a second environment where the first environment is rotating with respect to the second environment. The rotary union includes a pedestal (38) having a longitudinal pedestal bore (50) for transmitting fluid through pedestal (38); a housing (26) having a longitudinal housing bore (34) for transmitting fluid through housing (26). The diameter of longitudinal pedestal bore (50) of pedestal (38) is greater than the diameter of longitudinal housing bore (34) of housing (26). Housing (26) is coupled to the first environment and pedestal (38) coupled to the second environment; and rotating support structure (58, 60) is provided for coupling housing (26) and pedestal (38) with a gap (70) formed between a top portion of pedestal (38) and housing (26) with rotating support structure (58, 60) disposed below the gap with respect to the applicable gravity field.

Abstract: A system (30) and method for preheating molding compound in the form of resin pellets (20) used in molding integrated circuits (50). A slanted plate (36) is connected to an electrode (31) to preheat resin pellets (20). The slanted plate (36) produces a temperature gradient in pellets (20) with a high temperature end (21) and a lower temperature end (22). A preheated pellet (20) with the lower temperature end (22) first is placed in a mold pot (40). A transfer ram (46) contacts the high temperature end (21) of the pellet (20) to deform the pellet (20) and fill any void spaces between the pellet (20) and surrounding mold pot bushing (44). The ram (46) continues to deform the pellet (20) to force air or other gases from the mold pot bushing (44) and to inject molding compound into a mold cavity (42).

Abstract: A process is disclosed for inhibiting undesired diffusion of implanted dopants during and after dopant activation, as can occur during source/drain anneal. Undesired dopant diffusion is minimized by a dopant blocking layer, which is applied to the semiconductor body prior to dopant activation, and preferably prior to dopant implantation. The composition of the blocking layer is selected in accordance with the diffusion mechanism of the dopant to be implanted so that the concentration of lattice vacancies or interstitials (depending upon the dopant diffusion mechanism) is reduced, thereby inhibiting undesired migration of the implanted species.

Abstract: A source of equally spaced timing signals which includes a first signal source providing a first signal tracing an essentially exponential voltage curve, a second signal source including a transistor having a control electrode and an electron flow path therethrough having a voltage drop V.sub.BE thereacross, a voltage source providing a voltage V.sub.CC coupled to one end of the electron flow path, a resistance R.sub.L coupled between the control electrode and the voltage source, the other end of the flow path providing a second voltage signal in accordance with the equation V.sub.i =V.sub.H -I.sub.i R.sub.L for i=1 to n where I.sub.i =(V.sub.H /R.sub.L)(1-e.sup.-i.alpha.) and V.sub.H =V.sub.CC -V.sub.BE and a comparator providing a timing signal whenever the second voltage signal is greater than the first signal.

Abstract: A base cell for a CMOS gate array is provided with a first plurality of N-channel transistors 12, 14, 16 with two such N-channel transistors coupled in series. A first plurality of P-channel transistors 50, 52, 54 with two such P-channel transistors coupled in series. These transistors are interconnected at the transistor level to form a partially prewired circuit. Additional pairs of series connected N-channel transistors (18, 20), (22, 24) and pairs of series connected P-channel transistors (56, 58), (60, 62) are also provided and are interconnected at the transistor level to form additional partially prewired circuits. By adding additional levels of wiring 100, 102, the base cell can be finally wired to form a plurality of different logic circuits.

Abstract: A field programmable gate array (10) having a plurality of logic modules (31-35) has a pair of driver circuits (51-52) connected between each logic module (31) and logic module interconnection tracks or lines (12-16, 20-23) (51-52). Each of the drivers (51-52) has an input connected to receive a common output signal from the associated logic module (31). The output from each of the driver circuits (51-52) is selectively connectable to one of the interconnection tracks by a different respective antifuse (27). The output of each driver circuit (51-52) has a current magnitude less than a level that would damage the antifuse (27) but greater than a predetermined level, so that the track capacitances can be charged as rapidly as possible to increase the propagation time of a signal in the array. In one embodiment (10), the respective logic module interconnection lines or tracks 12 to which the pair of antifuses are connected are different logic module interconnection lines (12, 13).

Abstract: The invention is to a polishing pad 14 that has a polishing surface 19 in which portions 17 and 18 of the polishing surface 19 have been removed. The removed areas 17 and 18 are annular rings adjacent an outer 15 and inner 16 edges of the polishing pad 14. The non-polishing surfaces 18 and 19 taper 17a and 18a downward from the polishing surface 19.

Abstract: A N-channel MOS random access memory of the one transistor type is disclosed. The cell utilizes an ion implanted area beneath the capacitor dielectric to permit lower bias voltages on the capacitor. In one example, two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitor, and the other for the gate of the MOS transistor and to connect the gate to the bit select line. The capacitor dielectric may be formed of thermal SiO.sub.2 which is about half as thick as the gate insulator of the MOS transistor in the cell. In another example, a single-level poly cell uses an implanted region for the same purpose; the capacitor dielectric is the same thickness as the MOS gate insulator so the lower bias voltage functions to reduce stress failures of the dielectric.