Abstract: A low-profile, high power ball grid array, or land grid array, device including a plastic tape having first and second surfaces, a portion of the first surface covered with an adhesive layer. First and second openings are stamped through the tape and adhesive layer, the first openings configured for solder balls and the second openings configured to accommodate circuit chips. A copper foil is laminated on the adhesive layer, and the portion of this copper foil in the second openings is mechanically shaped into a position coplanar with the second surface, whereby it becomes useable as a chip mount pad, exposed after encapsulation for low resistance heat dissipation. The circuit chips are mounted by means of a thermally conductive material on each of the chip mount pads. Encapsulating material surrounds the mounted chips in low profile. For ball grid array devices, solder balls are attached to the copper foil exposed by the first openings in the tape.

Abstract: A method of fabricating an electrically conductive via and an SOI structure and the structure. A substrate and a device wafer are provided and an electrically insulating layer having an outer face is formed on one of the substrate or device wafer. The insulating layer has an electrical interconnect structure therein, a portion extending to the outer face of the insulating structure. The outer surface of the insulating layer is bonded to the other of the substrate or device wafer. A portion of the insulating layer can be disposed between the interconnect structure and at least one of the substrate or device wafer with ultimate interconnection made by applying a voltage across the portion of the insulating layer sufficient to break down the portion of the insulating layer while maintaining the integrity of the remainder of the SOI structure. At least one of the device layer and substrate includes a bond region with the interconnect structure contacting the bond region.

Abstract: A method of protecting an interconnect is provided. The method includes forming an integrated circuit structure having an interconnect, and depositing vaporized benzotriazole on the interconnect.

Abstract: A personal information manager (PIM) has been provided for use in controlling telephone call message responses for a wireless communications network mobile station telephone. The PIM permits a telephone user to program a unique response for each calling party. Typical responses including the normal audible alert, automatically transferring the call to voice mail, and silent ringing with no voice mail, to name but a few options. In addition, the matrix of calling parties and corresponding message responses can be modified for different times of the day or circumstances. For example, the PIM can be programmed to deliver a different set of responses during normal work hours than the responses provided at night, or during a business meeting.

Abstract: A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. The first dopant penetrates the substrate to a depth that is less than the LDD junction depth. A second dopant is implanted into the substrate beyond the LDD junction depth to form a source/drain region. The implantation of the second dopant overpowers a substantial portion of the first dopant to define a floating ring in the LDD region that mitigates channel hot carrier effects.

Abstract: A semiconductor device package and a method of making the same are provided. The semiconductor device includes a package substrate, a layer of conductive material, a group of channels, and a chip. The package substrate has a top layer. The top layer has a group of conductive vias formed therethrough. The conductive material layer is formed on the top layer of the package substrate. The group of channels are formed in the conductive material layer about at least some of the vias to define a group of contact pads on the vias. The chip is electrically coupled to the package substrate through the contact pads.

Abstract: A method of forming a membrane for use in conjunction with a semiconductor carrier and the membrane which includes an electrically insulating substrate and an interconnect pattern formed on the substrate. A stud is coupled to the interconnect pattern over the substrate by forming a gold ball, preferably by gold ball bonding techniques, and coating a portion of the gold ball with a compliant material, preferably an epoxy resin. The coating is filled with a material having sufficient hardness to be capable of penetrating the oxide film on the contact pads of semiconductor devices. The flakes are preferably silver or silver-based.

Abstract: A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. The first dopant penetrates the substrate to a depth that is less than the LDD junction depth. A second dopant is implanted into the substrate beyond the LDD junction depth to form a source/drain region. The implantation of the second dopant overpowers a substantial portion of the first dopant to define a floating ring in the LDD region that mitigates channel hot carrier effects.

Abstract: A scheme to provide a spectral view of the signals present at the customer premises equipment by the network operator and includes a digital signal processor (DSP) or other signal processing apparatus integrated into a customer premises equipment (CPE) tuner in which the DSP or other signal processing apparatus is operational to perform a spectral analysis.

Abstract: A thin film resistor structure and a method of fabricating a thin film resistor structure is provided. The thin film resistor structure includes an electrical interface layer or head layer that is a combination of a Titanium (Ti) layer and a Titanium Nitride (TiN) layer. The combination of the Ti layer and the TiN layer mitigates resistance associated with the electrical interface layers.

Abstract: Apparatus and methods for applying solder paste to circuits, such as integrated circuits, are disclosed. The apparatus and methods comprise a squeegee blade having a pair of elongated face sides spaced apart by a selected thickness and a corresponding pair of elongated substantially parallel narrow sides spaced apart by a selected width. The elongated face sides and elongated narrow sides join together to form squeegee operating edges. The squeegee blade is free of mounting aperture as to provide four operating edges. The squeegee blade is mounted to a resilient clamping structure which applies a regular and controlled gripping force so as to avoid deformation of the squeegee blade edge due to excessive mounting force. The plurality of fasteners are received by the clamping structure for adjusting the gripping force to the squeegee blade.

Abstract: The invention provides a method and device for building one or more passive components into a chip scale package. The method includes the steps of selecting a passive component having a terminal pitch that is a multiple of the package ball pitch of a chip scale package and mounting the selected passive component terminals to ball sites of the package. A preferred embodiment of the invention uses a single metal layer polyamide tape as the substrate of the package. Additional preferred embodiments of the invention are disclosed in which the terminal pitch multiple of the package ball pitch is one or two. Devices corresponding to the disclosed methods are also disclosed.

Abstract: A method for forming a SOI structure in which porous silicon is sealed and an epitaxial layer is grown thereover, followed by implantation of oxygen and annealing.

Abstract: An integrated circuit chip 501 has a plurality of contact pads (FIG. 5B) to be connected by reflow attachment 510 to outside parts. The chip comprises a deposited layer 505 of nickel/titanium alloy on each of the pads; the alloy has a composition and crystalline structure operable in reversible phase transitions under thermomechanical stress, whereby mechanical strain is absorbed by the alloy layer. Preferably, the alloy has between 55.0 and 56.0 weight % nickel, between 44.0 and 45.0 weight % titanium, and a thickness in the range from 0.3 to 6.0 ?m, recrystallized after deposition in a temperature range from 450 to 600° C. for a time period between 4 and 6 min. A layer 506 of solderable metal is on the alloy, operable as diffusion barrier after reflow attachment.

Abstract: A CDMA receiver is provided which is operable to receive a CDMA encoded signal and decode the information therein utilizing a selected code. The systems utilizes a plurality of multiply-accumulation blocks (40) which are operable to receive the signal and compare the received signal with a Walsh-Hadamard code. The comparison and the accumulation is made only in the middle of a chip clock with the edges thereof blanked. This information in the middle of the chip clock is accumulated in an accumulator, the MAC (40), for a symbol period. This is then compared with a look up table and then a decision made as to the logic value thereof.

Abstract: The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that it can perform correction of errors in stored data without increasing the circuit size and power consumption, and without decreasing operating speed. An error correction code EC corresponds to data stored in sub-memory 120 separate from main data stored in main memory 110. In read mode, the main data and error correction code are read from the main memory and sub-memory, respectively. On the basis of these data, the error correction code is generated for correcting errors in the read data. Error correction circuit 300 corrects errors in the main data. By storing the error correction code in a sub-memory different from the main memory and selecting the appropriate layout of the main memory and sub-memory, it is possible to increase the reading speed of the error correction code and to suppress time delays caused by error correction.

Abstract: A system and method implements optimal task partitioning between a general purpose processor (GPP) and a digital signal processor (DSP) to replace a fixed function ASIC solution with an OMAP software solution to implement a 3G phone that uses OMAP and requires MIDI synthesis, yielding a reduced system cost.

Abstract: An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. The network relocates most of the conventional power distribution interconnections from the circuit level to the newly created surface network, thus saving substantial amounts of silicon real estate and permitting shrinkage of the IC area. The network is electrically connected to selected active components by metal-filled vias; since these vias can easily be redesigned to other locations, IC designers gain a new degree of design freedom.

Abstract: A broken trim die tool detection sensor. The lands of the tie bar die connect with the leads of the unit to form switches. The states of these switches indicate broken die lands or other malfunctions.

Abstract: A digital-to-analog converter (DAC) error suppression arrangement suppresses DAC error arising from mismatched elements contained in a DAC (640 and/or 645) that is part of a modulator (FIG. 6). A low pass averaging (LPA) index decoder 650 controls a shifting arrangement 635 to shift a digital word T2 derived from modulator output Y so that the DAC error distribution constitutes a low pass profile (FIG. 5). Thus, DAC error is suppressed at higher frequencies (close to half the sampling rate), thereby providing improved spurious free dynamic range (SFDR). The LPA index decoder 650 causes the shifting arrangement 635 to shift the digital word T2 using only a single pointer per clock cycle.