Abstract: Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure (406, 506) within a semiconductor device (400, 500). The device typically comprises a first interconnect (402, 502), and a second interconnect (404, 504). The primary structure is disposed between the first and second interconnects to electrically intercouple them. An active diffusion volume (410, 514) is determined, within which the primary structure is located. A buffer structure (408, 508) is disposed upon the first interconnect in proximity to the primary structure and adapted to buffer the primary via structure from diffusive voiding occurring at a contact point between the primary structure and the first interconnect.

Abstract: Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically generated to implement the network within area constraints. After the selection of the number of rows of network elements, the number of elements in each row, the sequencing of the elements, and the element locations, are systematically determined. The network layout systematically produced reduces the influence of unfavorable factors on the network such as temperature gradients, process gradients, and interference, by dispersing subnetwork elements throughout the layout.

Abstract: A digital-to-analog converter (DAC) error suppression arrangement suppresses DAC error arising from mismatched elements contained in a DAC (640 and/or 645) that is part of a modulator (FIG. 6). A low pass averaging (LPA) index decoder 650 controls a shifting arrangement 635 to shift a digital word T2 derived from modulator output Y so that the DAC error distribution constitutes a low pass profile (FIG. 5). Thus, DAC error is suppressed at higher frequencies (close to half the sampling rate), thereby providing improved spurious free dynamic range (SFDR). The LPA index decoder 650 causes the shifting arrangement 635 to shift the digital word T2 using only a single pointer per clock cycle.

Abstract: A method and system for generating a video image is disclosed in which an object is monitored with a video camera to produce a sequence of video frames. Each of the video frames is divided into a plurality of regions, each region being representative of a portion of said object. For example, the frame of the video image may include the head and shoulder region of a user. Regions corresponding to predetermined facial features may be selected, such as the chin, opposing edges of the mouth, the nose, and the outer edge of each eye. At least one of the plurality of regions is selected. In the illustrative example, the selected region may comprise the mouth of the monitored user. The selected region is then recombined with each of the remaining regions of the video frame to form a display video image.

Abstract: An integrated circuit chip 501 has a plurality of contact pads (FIG. 5B) to be connected by reflow attachment 510 to outside parts. The chip comprises a deposited layer 505 of nickel/titanium alloy on each of the pads; the alloy has a composition and crystalline structure operable in reversible phase transitions under thermomechanical stress, whereby mechanical strain is absorbed by the alloy layer. Preferably, the alloy has between 55.0 and 56.0 weight % nickel, between 44.0 and 45.0 weight % titanium, and a thickness in the range from 0.3 to 6.0 ?m, recrystallized after deposition in a temperature range from 450 to 600° C. for a time period between 4 and 6 min. A layer 506 of solderable metal is on the alloy, operable as diffusion barrier after reflow attachment.

Abstract: Digitizing a signal includes sampling and holding an analog signal to yield a sampled signal, where the analog signal includes information. The sampled signal is filtered at a passive filter circuit to yield a filtered signal. The passive filter circuit includes at least one passive element and the filtered signal is characterized by a bandpass response. The filtered signal is quantized to yield a digital signal, where the digital signal corresponds to the analog signal and the digital signal includes the information.

Abstract: A digital tuning circuit which generates a digital code representative of a difference of signals generated by a mirror trans-conductor circuit (having electrical characteristics similar to a trans-conductor circuit in a filter) and a reference circuit. The digital code is used to adjust the trans-conductance of both the mirror trans-conductor circuit and the filter. Some of the most/more significant bits may be used to selectively activate the respective trans-conductor elements contained in the mirror trans-conductor circuit and the filter. The remaining bits may be used to fine-tune the trans-conductance of the trans-conductor elements and the filter.

Abstract: An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. The network relocates most of the conventional power distribution interconnections from the circuit level to the newly created surface network, thus saving substantial amounts of silicon real estate and permitting shrinkage of the IC area. The network is electrically connected to selected active components by metal-filled vias; since these vias can easily be redesigned to other locations, IC designers gain a new degree of design freedom.

Abstract: An apparatus for and method of extending the dynamic range of a RF communications receiver. The invention provides a mechanism for controlling the gain of both the LNA and down conversion mixer in the front end portion of an RF receiver. Both the LNA and the mixer are adapted to have both low and high gain modes of operation. The control mechanism typically comprises a two bit gain control that places both the LNA and mixer in one of four operating gain mode states. The selection of the most appropriate operating gain mode state, is preferably determined in accordance with various metrics such as the received levels of the desired signal, levels of interference signals, bit error rate and receiver RSSI.

Abstract: Disclosed is a method for generating patterns to be used in a spatial light modulator having a plurality of pixels. The method includes generating an optical pattern to be placed upon the pixels of the spatial light modulator, applying the optical pattern to the pixels of the spatial light modulator, measuring the optical performance of the plurality of pixels having the optical pattern applied to it, comparing the measured optical performance to a target optical performance, and adjusting the optical pattern applied to the plurality of pixels to form another optical pattern that more closely achieves the target optical performance.

Abstract: The invention is a leadframe/stabilizer (35) for use with semiconductor devices. Stabilizer (35) is for stabilizing the space between of lead frame leads (36–39) and improving the lead to lead spacing and to improve lead tip planarity. Stabilizer (35) extends partially along the length of and on each side of said lead frame leads (36–39) and include a die pad mount (40), integral with and forming a part of said stabilizer 35.

Abstract: The present invention provides methods of manufacturing a MEMS assembly. In one embodiment, the method includes mounting a MEMS device, such as a MEMS mirror array, on an assembly substrate, where the MEMS device has a sacrificial layer over components formed therein. The method also includes coupling an assembly lid to the assembly substrate and over the MEMS device to create an interior of the MEMS assembly housing the MEMS device, whereby the coupling maintains an opening to the interior of the MEMS assembly. Furthermore, the method includes removing the sacrificial layer through the opening. A MEMS assembly constructed according to a process of the present invention is also disclosed.

Abstract: A package for an electrical device having at least one connection locus for providing selected electrical access to the device includes: (a) a substrate having an accommodation site; (b) at least one electrically conductive mass arranged with the substrate in a neighboring relationship with the accommodation site; (c) at least one connection structure coupling the at least one connection locus with the at least one conductive mass when the device is situated at the accommodation site in an assembled orientation; and (d) an enclosing structure substantially enclosing the device and a portion of the substrate. The enclosing structure and the at least one conductive mass cooperate to present at least one contact structure accessible from exterior of the enclosing structure configured for effecting surface mounting of the package in a circuit.

Abstract: A voltage controlled oscillator (600) includes a voltage to current portion (400) that is inversely proportional to the semiconductor processing in order to compensate for variations both in the low-frequency and high-frequency portions of the VCO gain response. To compensate for low-frequency variations, a portion of the control current (ICTL), non-compensated control current ICTLNC (436), is subtracted from a reference current IREF (408) and the result, a low-frequency compensating control current, ICTLLF (438), is added to the non-compensated control current ICTLNC (436). To compensate for high frequency variations, a number of differential transistor pairs (410-416) are provided that have tail currents that are inversely proportional to the processing. One input (426) to all the differential pairs is connected to the VCO's control voltage while the other inputs (418-424) are connected to successively increasing voltages in the control voltage range.

Abstract: In one embodiment, a method for wavelet analysis of one or more acoustic signals to identify one or more anomalies in an object includes receiving an acoustic signal from an acoustic scan of an object and calculating a wavelet power spectrum of the acoustic signal. The method also includes accessing a library of one or more reference wavelet power spectra that each correspond to one or more objects that comprise one or more known anomalies and comparing the wavelet power spectrum with one or more reference wavelet power spectra. If the wavelet power spectrum from the acoustic scan corresponds to one or more reference wavelet power spectra, analysis results are communicated indicating that the object under analysis comprises one or more particular known anomalies corresponding to the one or more reference wavelet power spectra that correspond to the wavelet power spectrum.

Abstract: A analog-to-digital converters and second order noise shaping systems are presented for providing a noise shaped analog feedback signal to a A/D converter in an analog-to-digital conversion system. The noise shaping system comprises a first order integrator having a single amplifier, and a digital error feedback system comprising a digital signal processing system, in which the digital error feedback system provides an analog feedback signal to the A/D converter with second order noise shaping with respect to a quantization error associated with the A/D converter.

Abstract: A method of reducing package stress includes placing matched components of an op-amp substantially in a region of a die having the least stress gradients. The region is located in the center of the die. Further, the center is the common centroid of the die. The matched components are the current mirror input stages of the op-amp. In one embodiment, a semiconductor configuration includes a die having a region with the least stress gradients, and an op-amp containing matched components that are located substantially in the region.

Abstract: A memory traffic access controller (18) responsive to a plurality of requests to access a memory. The controller includes circuitry (18d) for associating, for each of the plurality of requests, an initial priority value corresponding to the request. The controller further includes circuitry (18b, 18d, 18e, 18f) for changing the initial priority value for selected ones of the plurality of requests to a different priority value. Lastly, the controller includes circuitry for outputting (18d) a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value.

Abstract: A low noise multi-loop radio frequency synthesizer receives an input reference signal having a frequency fR, into a fine tune PLL and a coarse tune PLL. The fine tune PLL outputs a fine tune signal with a frequency fR?P, P beings an integer, while the coarse tune PLL outputs a coarse tune signal with frequency fR?A, where A is an integer. A translation PLL has a unity multiplication factor and is driven by the fine tune signal output. The frequency synthesizer has a Gilbert cell double balanced mixer coupled between the coarse tune and the translation PLLs, the Gilbert cell mixer combining the coarse tune signal and the output signal of the translation PLL and coupling the mixed signal into the translation PLL. The translation loop outputs a signal with a frequency proportional to the linear sum of the coarse tune signal and the fine tune signal.

Abstract: A method and apparatus for enabling z-axis offset of narrow metal ties straps in lead frames used for packaging integrated circuits to prevent bowing or distortion. Simultaneous offsetting of the tie strap and stress relief mechanisms are provided on both the front and back sides of the lead frame. Those mechanisms include indentations along the long or primary axis of each tie strap, coupled with depressions across the top surface both at the center of the lead frame and between the base of the off set and the chip attach locations to prevent bowing in small pad and no pad lead frames, in particular.