Abstract: This application describes a method of protecting data and program code stored in an EPROM array from piracy. The security scheme allows for segmentation of the array to protect one section of the array from reading while programming a non-secure section. The security scheme also allows for protection of the entire array after programming is complete. It also incorporates a device to prevent tampering with the segmentation registers and a means to prevent circumvention of the security scheme even when the processor is in one or more of its test modes.

Abstract: An IEEE 1394 serial bus, during bus initialization, transmits a plurality of self-ID packets across the bus. Each node on the bus is operable to receive the self-ID packet from the bus (140) via receiver (146). Asynchronous packets and isochronous packets are stored in a FIFO (166) for later use by a host interface (150). The self-ID packets are verified by a hardware circuit (170) that provides verification of the self-ID packets as they are received without requiring the software to later evaluate the self-ID packets from storage in the FIFO (166). If an error is determined, this is stored in registers (164) for later processing by the host interface (150).

Abstract: A plastic packaged integrated circuit (20) having a thick copper plated top surface level interconnection structure. A semiconductor integrated circuit (20) is formed having devices at the surface of a semiconductor substrate (23). First and second metallization layers (27, 31) are formed over the substrate and contacting selected ones of said devices. The first and second levels of metallization may be in contact with one another through vias. A thick top surface level metal interconnect layer (35) is then formed over the second metal layer (31), either physically contacting it or selectively electrically contacting it. The surface level metal (35) is fabricated of a highly conductive copper layer. The thick surface level metal layer (35) substantially lowers the resistance of the interconnect metallization of the device (20) and further eliminates current debiasing and early failure location problems experienced with integrated circuits of the prior art.

Abstract: A plastic packaged integrated circuit (20) having a thick copper plated top surface level interconnection structure. A semiconductor integrated circuit (20) is formed having devices at the surface of a semiconductor substrate (23). First and second metallization layers (27, 31) are formed over the substrate and contacting selected ones of said devices. The first and second levels of metallization may be in contact with one another through vias. A thick top surface level metal interconnect layer (35) is then formed over the second metal layer (31), either physically contacting it or selectively electrically contacting it. The surface level metal (35) is fabricated of a highly conductive copper layer. The thick surface level metal layer (35) substantially lowers the resistance of the interconnect metallization of the device (20) and further eliminates current debiasing and early failure location problems experienced with integrated circuits of the prior art.

Abstract: A programmable fast comparison circuit for determining whether the result of a logic operation on two operands is the same as a specified number in advance of the completion of the actual operation includes four fast compare units coupled to each operand signal pairs of the same degree of significance for identifying possible result signal pairs of the same degree of significance. Each fast compare circuit generates a positive signal when a result signal pair is possible based on the corresponding operand bit signal pairs. Control signals determined by the specified number signal pair of the same degree of significance is used to activate one of the four fast compare circuits with the corresponding result signal pair. When the fast compare circuit activated by the control signals is a circuit generating a positive signal, the positive signal is transmitted to a combinatorial circuit.

Abstract: An isolation structure is provided that includes a substrate (10), a refill material such as a refill oxide (22), a gate dielectric such as a gate oxide layer (24), and a gate conductor layer such a polysilicon gate layer (26). The substrate (10) has an active region (12), an active region (14), and a trench region provided between the active region (12) and the active region (14). The active region (14) includes a top corner (32) that is provided where an upper surface of the active region (14) and the trench wall of the trench region that is adjacent to the active region (14) meet. The refill oxide (22) is positioned within the trench region and extends to cover at least a portion of the top corner. The gate oxide layer (24) is provided on the upper surface of the active region (14). The polysilicon gate layer (26) is provided on an upper surface of the gate oxide layer (24).

Abstract: A metal-poly stack gate structure and associated method for forming a conductive barrier layer between W and poly in the metal-gate stack gate structure. The process includes the steps of depositing doped silicon on a substrate; forming nitride on the deposited silicon; depositing a metal on the nitride to form a metal/nitride/deposited silicon stack; and thermally treating the stack to transform the nitride into a conductive barrier layer between the metal and the deposited silicon. The thermal treatment transforms the nitride layer (SiN.sub.x or SiN.sub.x O.sub.y) into a conductive barrier (WSi.sub.x N.sub.y or WSi.sub.x N.sub.y O.sub.z) to form a W/barrier/poly stack gate structure. The barrier layer blocks reaction between W and Si, enhances sheet resistance, enhances adhesion between the W and the poly, and is stable at high temperatures.

Abstract: A method for operating a scan-line video processor that allows for vertical scaling with no additional memory in a display system and extracts more SVP instructions in vertical down scaling applications. The input and output sync periods of the SVP (16) are controlled such that the SVP (16) produces output lines of interpolated data that is a vertical scaling factor of the input lines. The data is then sent to a memory (24) to correct for centering and time base changes in the interpolated data. Finally, the data is sent to a display device, such as a CRT or a spatial light modulator.

Abstract: A ten transistor low voltage, low power static random access memory cell (10) includes a first inverter (12) cross-coupled to a second inverter (18). A series combination of a first pass transistor (24) and a first bitline select transistor (28) is connected between an output node (13) of the first inverter (12) and a first bitline (36). A first write pass transistor (32) is placed in parallel with the first pass transistor (24). A series combination of a second pass transistor (26) and a second bitline select transistor (30) is connected between an output node (17) of the second inverter (18) and a second bitline (38). A second write pass transistor (34) is placed in parallel with the second pass transistor (26).

Abstract: The invention comprises a transistor having a self-aligned implant under the gate. The transistor comprises a drain region, a source region opposite the drain region, and a channel region in a semiconductor substrate extending between the source region and the drain region. A front gate is disposed outwardly from the first substrate layer and is separated from the channel region by a dielectric layer. The front gate comprises a first gate layer disposed outwardly from the dielectric layer and a second gate layer disposed outwardly from the first gate layer. A self-aligned implant region is disposed inwardly from the channel region and in approximate vertical alignment with the front gate.

Abstract: A high voltage DENMOS transistor (10) having improved ESD protection. The transistor (10) is optimized to provide maximum substrate current in order to turn on the inherent lateral npn transistor during an ESD event so that the lateral npn can dissipate the ESD event without damage to the transistor (10). This is accomplished by optimizing the overlap (A) of the drain extended region (16) and the gate electrode (28) to control the gate coupling to achieve maximum substrate current.

Abstract: An improved mold system (20) is provided. The mold system (20) includes a mold (30) having at least one mold cavity (28). A pot (22) is connected to each of the mold cavities (28) through a runner system (24). A bellows container (50) containing a molding material (60) is disposed with the pot (22). A plunger (31) applies a compressive load to the molding material (60) contained with the bellows container (50) to force the molding material (60) through the runner system (24) into the mold cavities (28).

Abstract: An input architecture for supply a plurality of signals to a plurality of circuit blocks located in an interior of an integrated circuit device. A plurality of unbuffered signal lines are each connected between a bondpad area and all of a plurality of input buffers. The input buffers are located adjacent to and connected to the plurality of circuit blocks instead of being located at the periphey of the integrated circuit adjacent the bondpad area.

Abstract: A method for forming a MOSFET transistor (100) using a disposable gate (120). A disposable gate (120) having at least two materials (122,124) that may be etched selectively with respect to each other is formed on a semiconductor substrate (102). Source/drain regions (104) are then formed adjacent the disposable gate. The source/drain regions may, for example, include raised source/drain regions (106). An insulator layer (114) is then deposited over the structure and then a portion of the insulator layer (114) over the disposable gate (120) is removed (e.g., using CMP or an etch-back). The composition of the insulator layer (114) is chosen such that the top layer (124) of the disposable gate (120) may be removed selectively with respect to the insulator layer (114). The disposable gate (120) is then removed and a channel implant may be performed that is self-aligned and only in the channel region. The gate dielectric (110) and gate electrode (112) are then formed.

Abstract: An electronic device includes an integrated circuit chip, an interposer and a printed circuit board. A first ball connector is used to connect the interposer to printed circuit board. The interposer may be connected to the integrated circuit chip by a second ball connector or a wire bond. The first ball connector is disposed on a cantilever structure formed in the interposer. The cantilever is formed by creating a channel in the interposer. The cantilever absorbs stress caused by a difference between the thermal expansion of the integrated circuit chip as compared to the printed circuit board. The cantilever thus reduces stress in the ball connector by allowing the ball connector to move within a plane defined by the interposer.

Abstract: A method for forming a MOSFET (200) using a disposable gate. A disposable gate (220) having at least two materials that may be etched selectively with respect to each other is formed on a substrate (202). A sidewall dielectric (215) is formed on the sidewalls of the disposable gate (220). The composition of the disposable gate materials (222,223, and 224) and the sidewall dielectric (215) are chosen such that the disposable gate (220) may be removed selectively with respect to the sidewall dielectric (215). A dielectric layer (214) is then deposited over the structure and a portion of the dielectric layer (214) is removed to expose the disposable gate (220) (e.g., using CMP or an etch-back). The composition of the dielectric layer (214) is chosen such that (1) the dielectric layer (214) may be removed selectively with respect to the sidewall dielectric (215) and (2) a layer of the disposable gate (220) may be removed selectively with respect to the dielectric layer (214).

Abstract: A LDMOS having improved ESD reliability and a method for designing such a LDMOS. A higher gate clamp voltage and/or minimized drain clamp voltage is used to maximize the ESD performance of the LDMOS. Given a set of design parameters, one or more of the gate clamp voltage, drain clamp voltage, or size of the LDMOS are optimized to meet the design parameters while achieving the optimum ESD performance.

Abstract: A method is provided for improving the texture of a metal interconnect (32) in a semiconductor device (10). A first layer of titanium (24), a layer of titanium nitride (26), a second layer of titanium (28), and a metal film (30) are sequentially formed over an oxide layer (12). The second titanium layer (28) is preferably out 10-20 nm thick. Because the metal film (30) is formed over the second titanium layer (28), any metal interconnect (32) that is formed as a part of the metal film (30) has a strong (111) crystalline orientation. Furthermore, because the second titanium layer (28) is relatively thin, the metal film (30) and metal interconnect (32) are not completely transformed into a metal compound having a high electrical resistance.

Abstract: A method of fabricating a transistor having an improved salicided gate is provided. The method may include forming a gate (14) that is separated from a substrate (12) by a gate insulator (16). A spacer (22) may be formed proximate the gate (14) such that the spacer (22) exposes a top region (28) and a side region (30) of the gate (14). The top region (28) and the side region (30) of the gate (14) may be irradiated at an angle (38) to form a post amorphous region (32) within the gate (14). A reactive layer (42) may be formed adjacent the post amorphous region (32). A salicidation region (44) may be then formed between the post amorphous region (32) and the reactive layer (42). The reactive layer (42) may be removed to expose the salicidation region (44).

Abstract: Method of forming a salicide on a gate structure uses sidewall spacers which leave at least 30 percent of the gate sidewall exposed. After metal deposition, which has at least 50 percent step coverage, an anisotropic etch removes some or all of the metal on horizontal surfaces. Silicides formed from this metal layer are conformal, or even thicker on the sides of the gate than on horizontal structures. This achieves low sheet resistance on the gate, while remaining compatible with shallow junctions.