Abstract: Filtering image information to generate a dithered image includes receiving input image information corresponding to an image generated using a first array comprising a first number of smaller pixels. Intermediate image information is generated from the input image information. The intermediate image information is generated to produce the image using a second array comprising a second number of larger pixels, where the second number less than the first number. A frequency response associated with the image produced using the second array exhibits effects. The intermediate image information is repeatedly filtered to generate updated image information from the intermediate image information and to compensate for the effects. Sub-image information is generated from the updated image information, the sub-image information corresponding to a dithered image.

Abstract: The disclosed embodiments combine an electrothermal actuator system with an electrostatic attraction system, in order to orient bistable micromirrors in digital micromirror devices (DMDs). The micromirror, pivotally supported, can switch between two orientations. While typical DMD systems use electrostatic electrodes to orient the micromirror, stiction forces can restrict micromirror motion, affecting optical performance. The disclosed embodiments use an electrothermal actuation system to mechanically assist the electrodes, overcoming stiction without the need for a high-voltage reset pulse.

Abstract: Disclosed herein is a microelectromechanical device having a structural layer composed of a low stress TiNx layer and a method of making the same.

Abstract: In a test and debug system, a plurality of trace streams, including a timing trace stream, are transmitted from the target processing unit to the host processing unit for analysis. The timing trace stream, the trace stream that indicates activity or non-activity of the program counter each clock cycle, can occupy a large percentage of the bandwidth of the transmitted data. The transmitted data is organized into groups of packets, each packet having a control signal portion and a payload portion. Each information packet has a logic signal stored at each location indicating an activity or a non-activity of the program counter. By identifying portion of the timing trace stream wherein the activity or non-activity does not change for one or more groups of timing packets, the information in a plurality of packets can be represented by a header and an information packet that describes a number of packets in which the activity or non-activity of the program counter does not change.

Abstract: Described is an optical device for combining multiple light sources in an optical projection system. One embodiment of the optical device includes at least two light sources having first and second wavelengths, and an optical element for substantially diffracting the first and second wavelengths of the two light sources and combining them into a single beam of light.

Abstract: A method for manufacturing a transistor includes providing a transistor assembly having a semiconductor layer with a first surface, a dielectric layer disposed on the first surface, a gate electrode disposed on the dielectric layer, an insulation layer adjacent at least part of the gate electrode, and a nitride spacer layer adjacent at least part of the insulation layer. The method also includes depositing, on part of the first surface, a material that will react with the semiconductor layer to form silicide and removing the unreacted material. The method further includes etching the nitride spacer layer, depositing a pre-metal spacer layer adjacent at least part of the nitride spacer layer and at least part of the first surface, etch removing a portion of the pre-metal spacer layer to expose part of the silicided portion of the first surface, and forming a contact with the silicided portion of the first surface.

Abstract: A method of fabricating a transistor that includes a doped buried region within a semiconductor body. The doped buried region includes a portion having a first thickness and a second thickness, the first thickness being less than the second thickness. In one embodiment, the first thickness is about half the second thickness. The transistor also includes a collector region over the buried region, a base region within the collector region and an emitter region within the base region.

Abstract: The invention provides a method and device for building one or more passive components into a chip scale package. The method includes the steps of selecting a passive component having a terminal pitch that is a multiple of the package ball pitch of a chip scale package and mounting the selected passive component terminals to ball sites of the package. A preferred embodiment of the invention uses a single metal layer polyamide tape as the substrate of the package. Additional preferred embodiments of the invention are disclosed in which the terminal pitch multiple of the package ball pitch is one or two. Devices corresponding to the disclosed methods are also disclosed.

Abstract: A high resolution programmable clock synthesizer that is portable across processes and, thus, process independent is disclosed herein. The clock synthesizer provides a dynamic solution, in that the frequency of the desired clock signal is programmable. Initially, a control unit monitors the input clock signal and the output clock signal to provide the appropriate control signals to a delay string buffer and a fine tuning unit based upon the desired frequency of the output clock signal. While the delay string buffer provides a coarse adjustment to the input clock signal, fine control is provided through the use of the fine tuning unit which further adjustments to the input clock signal. This clock synthesizer exceeds the accuracy of known delay line oscillators by using drive strengths of the in-loop elements to provide a better granularity for the clock synthesizer. Thereby, high resolution is achieved through the use of coarse adjustment and fine adjustment.

Abstract: A micromirror device and a method of making the same are disclosed herein. The micromirror device comprises a mirror plate, hinge, and post each having an electrically conductive layer. One of the hinge, mirror plate, and post further comprises an electrically insulating layer. To enable the electrical connections between the conducting layers of the hinge, mirror plate, and post, the insulating layer is patterned.

Abstract: Disclosed herein is an illumination system for use in display systems employing spatial light modulators. The illumination system comprises a fastening mechanism for securing the bonding of the walls of the light integrator of the illumination system. A heat dissipation mechanism can be alternatively provided for reducing the temperature of the illumination system by dissipating the heat thereof.

Abstract: A spatial light modulator is disclosed, along with methods for making such a modulator. The spatial light modulator comprises an array of micromirrors each having a hinge and a micromirror plate held via a hinge on a substrate, the micromirror plate being attached to the hinge such that the micromirror plate can rotate along a rotation axis and the hinge structure is located between the micromirror plate and the light source. The mirror plate is formed between the hinge and the substrate on which the hinge is formed. As a result, the hinge is exposed to the incident light during the operation.

Abstract: Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically generated to implement the network within area constraints. After the selection of the number of rows of network elements, the number of elements in each row, the sequencing of the elements, and the element locations, are systematically determined. The network layout systematically produced reduces the influence of unfavorable factors on the network such as temperature gradients, process gradients, and interference, by dispersing subnetwork elements throughout the layout.

Abstract: The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that it can perform correction of errors in stored data without increasing the circuit size and power consumption, and without decreasing operating speed. An error correction code EC corresponds to data stored in sub-memory 120 separate from main data stored in main memory 110. In read mode, the main data and error correction code are read from the main memory and sub-memory, respectively. On the basis of these data, the error correction code is generated for correcting errors in the read data. Error correction circuit 300 corrects errors in the main data. By storing the error correction code in a sub-memory different from the main memory and selecting the appropriate layout of the main memory and sub-memory, it is possible to increase the reading speed of the error correction code and to suppress time delays caused by error correction.

Abstract: A method of forming a film stack in an integrated circuit, said method comprising depositing a layer of silicon carbide adjacent a first layer of dielectric material, depositing a layer of silicon nitride adjacent the layer of silicon carbide, and depositing a second layer of dielectric material adjacent the layer of silicon nitride.

Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes forming fluorine containing regions (220) in the source/drain regions (190) employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer (310) over the substrate (110) and fluorine containing regions (220), and reacting the metal layer (310) with the fluorine containing regions (220) to form metal silicide regions (410) in the source/drain regions (190).

Abstract: A sigma-delta modulator includes a discrete time circuit that receives a digital feedback signal and an input signal, where the input signal includes information and one or more analog input currents. The discrete time circuit converts the digital feedback signal into an analog feedback signal during a first discrete time and sums the analog feedback signal and the one or more analog input currents during a second discrete time to yield one or more summed signals. A continuous time circuit includes passive elements, is coupled to the discrete time circuit, and operates to filter the one or more summed signals using a first-order filter and a second-order filter in order to generate one or more filtered signals. A quantizer is coupled to the continuous time circuit and generates the digital signal using the one or more filtered signals, where the digital signal comprising the information.

Abstract: The invention provides a method for quantifying over-etch of a conductive feature. In one embodiment, this method includes forming a conductive feature over a substrate, the conductive feature having a sheet resistance test structure associated therewith, the sheet resistance test structure having a first sheet resistance value. This method may further include etching the conductive feature and the sheet resistance test structure using a common etch process, obtaining a second sheet resistance value of the sheet resistance test structure after the etching, and quantifying an amount of over-etch into the conductive feature using the first and second sheet resistance values.

Abstract: According to an aspect of present invention, modules designed to operate with different frequency in functional (normal) mode are tested using a sequential scan based technique at the respective frequencies. In one embodiment the interface logic connecting the two modules is tested for at-speed performance (i.e., the same speed at which the interface would be operated in functional mode during normal operation).

Abstract: Methods and apparatus are provided for preventing charge accumulation in microelectromechanical systems, especially in micromirror array devices having a plurality of micromirrors. Voltages are applied to the micromirrors for actuating the micromirrors. Polarities of the voltage differences between mirror plates and electrodes are inverted so as to prevent charge accumulation.