Abstract: A transceiver device and method thereof for sending signals to and receiving signals from another device via a wireless connection and for providing information about the wireless connection to a user. An antenna coupled to the transceiver is visible to the user. The antenna is a lighted antenna that is adapted to provide a visual indication of a wireless signal to a user. The lighted antenna can be used to show that the transceiver is transmitting or receiving signals, that a data connection has been made, or that a Bluetooth piconet has been detected. The color and/or intensity of the lighted antenna can be varied to indicate, for example, the strength of the signal. With a lighted antenna, additional features and functionality can be incorporated into a transceiver device while maintaining the form factor of existing designs. The multi-functionality of a lighted antenna is particularly suited for smaller devices where space is at a premium.

Abstract: A method for efficient data transfers between domains of differing data formats. In one exemplary implementation, data transfer is performed with respect to an IEEE 1394 communication domain and an Ethernet communication domain. The novel data transfer method advantageously eliminates the need to copy the data payload section of a received data packet from one memory region to another memory region within a bridge device coupled between first and second communication domains. Specifically, the header, data payload and trailer sections of a received data packet (of a first communication domain format) are copied into a first portion of memory within the bridge device. The present invention then assembles a new data packet by constructing a new header of a second communication domain and appending a pointer to the new header that points to the data payload location within the first portion of memory.

Abstract: The present invention is drawn to a system for attaching and supporting a cable to an IO panel of an electronic component such as the IO back panel of a computer. The system is comprised of a cable dock coupled to an IO panel, with a gasket disposed within the cable dock to form a conducting path from the IO panel to the cable backshell. In particular, a cable dock is fixed to the IO panel where an IO connector is exposed. Once the cable backshell is plugged into the cable dock, the cable dock provides mechanical support for a cable assembly comprising the cable-end connector, the cable backshell and the cable. The cable assembly is secured by the cable dock rather than by the coupling made between the cable-end connector and the IO connector. The cable dock also orients the cable-end connector in coupling to the IO connector such that the cable backshell is prevented from being incorrectly plugged into the cable dock.

Abstract: A computer system provides dynamic memory allocation for graphics. The computer system includes a memory controller, a unified system memory, and memory clients each having access to the system memory via the memory controller. Memory clients can include a graphics rendering engine, a CPU, an image processor, a data compression/expansion device, an input/output device, a graphics back end device. The computer system provides read/write access to the unified system memory, through the memory controller, for each of the memory clients. Translation hardware is included for mapping virtual addresses of pixel buffers to physical memory locations in the unified system memory. Pixel buffers are dynamically allocated as tiles of physically contiguous memory. Translation hardware is implemented in each of the computational devices, which are included as memory clients in the computer system, including primarily the rendering engine.

Abstract: A computer implemented method for generating virtual files to provide more flexibility and efficiency in the sharing of data within a physical information file. In a computer system, a large physical file contains many separate data portions that need to be shared. In one case, the data portions can correspond to video and audio information of multi-media scenes. An application can need to jump within the physical file from scene to scene when composing user interactive multi-media applications, such as storybook applications. The present invention provides a mechanism allowing a user to define a virtual file containing certain data portions of the physical file. The user inputs an offset value representing a byte offset from the start of the data portion in the physical file and also the size of the data portion is input. The offset value, the size and the file name of the virtual file is recorded into an index file.

Abstract: A texture value determining (TVD) circuit approximates non-homogenous 2nd order perspective texture mapping to provide texture for a polygon using linear interpolation and input parameters. The TVD circuit of the present invention includes a vertical walk subcircuit and an orthogonal walk subcircuit. The vertical walk subcircuit determines texture coordinates, u(a.sub.0,n) and v(a.sub.0,n) that represent the pixels along a vertical main slop of a triangle polygon. The orthogonal walk subcircuit determines texture coordinates, u(a.sub.m,n) and v(a.sub.m,n), for orthogonally walked polygon coordinate positions for which m>0. The orthogonally walked coordinate positions represent individual scan lines. The vertical walk subcircuit of the TVD circuit includes adders, latches, and accumulators. Each element of the vertical walk subcircuit receives a vertical main slope clock (n-clock) signal. An output of the vertical walk subsystem is computed based on the relationship,u(a.sub.0,n)=u(a.sub.0, n-1)+du.sub.

Abstract: The optimization process of the present invention replaces the successive delay table generation approach of the prior art with one that minimizes delay table size by generating only those indices sufficient to satisfy the error limits prescribed. This is accomplished by generating only portions of the delay table by reducing the maximum load/ramp point for each generated portion until such time as the error percentage limit is not exceeded. The load/ramp indices for the generated delay tables are those defined for the interpolation comparison table. These non-linearly distributed indices force a greater indexing range within the higher load/ramp regions, where relative interpolation error percentage are not as great as those within the lower regions. Within the present invention, the maximum load/ramp point of the last optimized portion becomes the minimum of the next portion, while the maximum load/ramp of the interpolation table becomes the next max point.

Abstract: A method for creating a color filter on a display screen that allows better and more efficient adhesion of color pigment crystals to the screen display structure. In one embodiment, the present invention creates a color filter on a glass substrate having a pixel-defining structure. The present embodiment first creates a color filter slurry by mixing a polyvinyl alcohol solution with a color crystal pigment. The color filter slurry is then applied onto the interior surface of the display screen. The slurry is then dried. The dried color filter slurry is then exposed to an UV light from the exterior side of the display screen. The UV light exposes the color filter slurry through a photomask and through the display screen.

Abstract: The present invention comprises a system for efficiently using non-volatile memory in an embedded system. The system of the present invention includes an embedded system having a processor, a volatile memory, and a non-volatile memory. A decompression algorithm is stored in the non-volatile memory along with a main program. When the embedded system is powered up, the decompression algorithm is executed by the processor. The decompression algorithm operates on compressed software stored in the non-volatile memory. The compressed software includes data needed to initialize the main program. After the operation of the algorithm, the decompressed software is loaded into the volatile memory, thereby initializing the main program. Since the software for initializing the main program is stored in non-volatile memory in a compressed state, and since the decompression algorithm is compact, the present invention efficiently utilizes non-volatile memory space.

Abstract: A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board. The first and second SRAMs are coupled to the address line by respective cache buses. A processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line. In one embodiment of the invention, a heat sink is thermally coupled to the processor. The processor has a plurality of contact pads disposed thereon.

Abstract: A method and apparatus for optimizing sample fetching in a peripheral component interconnect (PCI) environment. In one embodiment the present invention generates a sample page base address corresponding to a first part of a first address received from a digital signal processor (DSP). The generated sample page base address is then stored in a sample page base address cache which can be accessed by the DSP without accessing a PCI bus. The first part of the first address is compared to a first part of a second address. Provided that the first part of the first address and the first part of the second address are the same, the present invention combines a second portion of the second address sent from the DSP with the generated sample page base address stored in the sample page base address cache. In so doing, the present invention generates a complete address of a sample to be fetched without accessing the PCI bus.

Abstract: A self-aligned contact etch and method for forming a self-aligned contact etch. In one embodiment, the present invention performs an oxide selective etch to form an opening originating at a top surface of a photoresist layer. The opening extends through an underlying oxide layer, and terminates at a top surface of a nitride layer which underlies the oxide layer. Next, the present invention performs a nitride selective etch to extend the opening through the nitride layer to an underlying contact layer. In the present invention, the nitride selective etch causes the photoresist layer to be etched/receded. The nitride selective etch of the present invention further causes the oxide layer to be etched at and near the opening at the interface between the photoresist layer and the oxide layer. As a result, the opening is rounded at the top edge thereof when the layer of photoresist is removed.

Abstract: A method for determining an improved position fix by performing postprocessing on a realtime differentially corrected GPS position. A remote rover unit containing a GPS receiver is used to determine a differentially corrected position according to measured pseudoranges and realtime pseudorange correction vectors is broadcast by a base station. The rover unit applies realtime corrections to measurements to determine a more accurate realtime differential position. It then stores the realtime differential position and the realtime pseudorange correction vector. Subsequently, postprocessing is performed to determine a postprocessed pseudorange correction vector. A difference vector representing the difference between the realtime pseudorange correction vector and the postprocessed pseudorange correction vector is then determined. This difference vector is applied to the realtime differential position to calculate a more accurate, improved position fix.

Abstract: A dual global positioning system (GPS) receiver navigation system. The system of the present invention includes a primary GPS receiver adapted to determine a first position. The primary GPS receiver is certified to a first integrity level and is further adapted to provide GPS navigation data to an external device. The system of the present invention also includes a secondary GPS receiver coupled to the primary GPS receiver. The secondary GPS receiver is certified to a second integrity level having less stringent requirements than the first integrity level. The secondary GPS receiver is adapted to determine a second position and monitor the primary GPS receiver to detect a fault condition by comparing the first position and the second position, such that the GPS navigation data is provided in accordance with the first certification level regardless of the second integrity level of the secondary GPS receiver.

Abstract: The present invention comprises a voltage controlled oscillator (VCO) circuit having high power supply noise rejection. The circuit of the present invention includes an amplifier having positive, negative, and output terminals. A VCO input is coupled to the positive terminal for receiving a control voltage. A replica circuit is coupled to the negative terminal. A replica source follower transistor is coupled to the output terminal and is also coupled to the replica circuit. The replica source follower transistor transmits a replica current from a power supply to the replica circuit and is controlled by the amplifier. The present invention also includes a first and second VCO cell. The first VCO cell and the second VCO cell are both coupled to the replica circuit and to each other and the second VCO cell includes a VCO output for transmitting a VCO output signal.

Abstract: The system of the present invention comprises a system for implementing a real time capability in peripheral devices. The system of the present invention functions with a computer system including a processor, a memory, and a video controller, each coupled to a system bus. A USB (universal serial bus) controller is also coupled to the system bus for interfacing peripheral devices on a USB cable to the computer system. A first and second register are included in the USB controller for storing a controller frame number and a controller frame remaining, and a second and third register are included in the peripheral device for storing a device frame number and a device frame remaining. The peripheral device is coupled to the USB controller via a USB cable. A screen reference register is coupled to receive the controller frame number and the controller frame remaining from the USB controller and is coupled to receive a reference signal from a video controller.

Abstract: A FIFO controller circuit for interfacing data from a device running at one clock speed so that it is compatible with another device or transmission medium running at a different clock speed. A write controller is used to control the writing of data into the FIFO. The write controller is clocked at a first clock speed. A read controller is used to control the reading of data from the FIFO at a second, different clock speed. A counter is incremented when data is written to the FIFO and decremented when data is read from the FIFO. Thereby, the counter represents an amount of memory within the FIFO that is currently available. The decrement signal is generated in the first clock domain and then synchronized to the second clock domain. This provides error-free interfacing, irrespective of any phase differences existing between the two clock signals.

Abstract: The present invention allows the behavior of a state machine to be readily modified by software after it has been fabricated in silicon. To perform these modifications, the present invention uses special patch registers, multiplexers, and comparators to bypass certain states within the sequence of states within the combinatorial logic of the state machine and/or add new state sequences. Each patch register stores a state to be patched, a next state, and outputs. The state to be patched is the state that will be modified, while the next state is the state the state machine transitions into from the state to be patched, and the outputs are the outputs generated and asserted by the state machine while within the next state. Many such patch registers can be used by the present invention to define many modifications. Using this patch mechanism, the present invention allows new states to be added and existing states to be removed from the sequence of states that the state machine cycles through.