Abstract: A method and system for helping a user perform tasks in software. Graphic elements (e.g., icons) are rendered and displayed regardless of which task is being performed. An element can be either active or inactive; user selection of an element with the element active initiates an action in response to the selection while user selection of the element with the element inactive will not initiate the action. Some elements are activated and other elements are deactivated according to which task is to be performed. The elements are selectively activated and deactivated to guide the user through the tasks according to the order in which the tasks are logically performed. The elements thus suggest an order for performing the tasks, guiding the user through the tasks without the need for a help utility such as a wizard.

Abstract: A housing for a portable hand held device such as a palmtop computer uses a torsional latching system. The housing is made of front and rear housing laminated housing members. The torsional latch arrangement works in conjunction with a plurality of latch fingers along the edge to attach the front housing laminate with the rear housing laminate. The torsional latch arrangement has a pair of L-shaped latch ribs that engage with a T-shaped latch member by torsion of the L-shaped latch ribs into engagement with pockets adjacent the T-shaped latch member prevent movement of the two housing laminates in relation to one another.

Abstract: A noninterfering multiply-MAC (multiply accumulate) circuit is described. The circuit is operational to perform a MAC (multiply accumulate) operation and to perform a multiply operation without interfering with the accumulate value of the MAC operation. The circuit includes a first register, a second register, a multiplier circuit, and an accumulate circuit. The first register is addressable using either a primary first address or an alias first address. Moreover, the second register is addressable using either a primary second address or an alias second address. The multiplier circuit performs a multiply operation to generate a product value based on the data in the first and second registers after a write operation to either the first register or the second register. The accumulate circuit performs an accumulate operation to generate an accumulate value if either the alias first address or the alias second address is used in the write operation.

Abstract: A computer implemented method for updating alt attribute values in a data set. The application includes a file server for storing one or more file sets. The server is communicatively coupled to an attribute engine. The attribute engine is also communicatively coupled to an attribute database, wherein image data from the file sets are stored. The attribute database is communicatively coupled to a browser via an attribute portal, wherein an editor can edit alt attribute text values. The attribute engine updates the image data contained in the attribute database, based upon data of images in the file set. The attribute engine also updates the file set based upon the alt attribute values in the attribute database. Thus an editor can add or change alt attribute values in the file set via a browser.

Abstract: A system where a production microcontroller is partially copied in a FPGA of an ICE to form a virtual microcontroller. The virtual microcontroller and the production microcontroller simultaneously and independently run a microcontroller code to be debugged at a high frequency. The debugging logic can substantially reside in the ICE and the ICE can perform all debugging functions. The debug interface, residing in the production microcontroller, can enable the production microcontroller to communicate with the ICE in low frequencies. The production microcontroller may request the ICE to lower its frequency when the production microcontroller encounters a halt due to outside events. A user may command resumption of the operation of both the production microcontroller and the virtual microcontroller when debugging of the codes is completed.

Abstract: A method and system for verifying and altering an area of an image to be photocopied prior to producing a copy. According to one embodiment of the present invention, an image capturing device is used to capture an image of items to be copied. A representation of this captured image is then displayed on a screen to be previewed by a user prior to producing a copy. A control unit of the present embodiment allows the user to alter the representation displayed on the display screen and to control the form and content of the copy produced. Alterations to the representation include, but are not limited to, elimination of certain portions (cropping), selection of certain portions for copying, rearranging by cutting and pasting, identifying areas to be copied in color, identifying areas to be copied as shaded and identifying areas to be copied in a different size. Further, the control unit will allow the user to edit the representation on the display screen.

Abstract: A method for tracking a user flow of Web pages of a Web site to enable efficient updating of the hyperlinks of the Web site. A Web page is accessed out of a plurality of Web pages of a Web site. A set of actions available to a user are determined for the Web page. A set of the next pages linked to the Web page are determined for the Web page. A set of rules are defined that modify the set of actions available to the user or the set of next pages linked to the Web page in accordance with an identity of the user. The set of actions, the set of next pages, and the set of rules are stored in a table data structure for the Web page to track a user flow of the Web page. The table data structure enables the user flow of the Web page to be changed by altering the corresponding set of rules in the table data structure for the Web page.

Abstract: A keyboard sled adapted to communicatively interact with a portable computer system. In one embodiment, the keyboard sled is comprised of an integral receiving portion adapted to mechanically and electronically receive a portable computer system. An interface connector is disposed within the receiving portion and adapted to provide a communicative link between the keyboard sled and a portable computer system, when a portable computer system has been inserted in the receiving portion. The keyboard sled further has at least one mounting hook disposed within the receiving portion for providing positive retention of a portable computer system when coupled with the keyboard sled. A keyboard portion also present on the keyboard sled and also coupled with the interface connector provides input keys. The keyboard sled is also comprised of an integral data storage access slot which is adapted to provide access to a data storage device receptacle of the portable computer system.

Abstract: A microcontroller provides protection to memory blocks in an embedded memory. A set of rules such as security levels mapped to memory blocks are stored in a nonvolatile supervisory memory. An algorithm for application of the rules is stored in a supervisory ROM. When a read or write operation is to be carried out, the rules are applied according to the algorithm in order to authorize or reject the read or write operation. Security levels can be modified, but only according to defined rules. In one embodiment, the security levels can only be increased.

Abstract: A method and system of periodically measuring the signal strength fluctuations in a wireless connection between a portable computer system and a wireless network. The portable computer system has a main processor and a DSP (digital signal processor). The DSP receives instructions from the main processor for controlling the periodic measuring, and subsequent thereto is placed in low power mode. The main processor is placed into a low power mode after sending the instructions. The DSP periodically awakens to measure the signal strength fluctuations while the main processor remains in a low power mode. When the signal strength fluctuation is unacceptable, this triggers the DSP to awaken the main processor. When the signal strength fluctuation is acceptable, the DSP returns to a low power state until the next periodic measuring.

Abstract: A system and method of testing switch functionality of a tunable capacitor array is disclosed. A built in test (BIT) circuit provides digital device for testing the functionality of a programmable switch capacitor array circuit. The method and system provides for switching a capacitor switch of a switch capacitor array between on and off, switching a test enable switch of a BIT circuit between on and off, pulling an internal node of the BIT circuit either high or low using a current source, and determining whether the internal node has been pulled either high or low. In addition, the method and system provides for making a pass or fail determination based on a determined state of the internal node.

Abstract: One embodiment of the present invention includes a microcontroller that enables its on-chip microprocessor to write data into a register of an on-chip programmable analog circuit even though the two circuits may be operating at different frequencies. Specifically, the microcontroller includes a write synchronization circuit that helps facilitate the write operation between these two circuits. For example, the write synchronization circuit is coupled to receive write cycle signals from the microprocessor and is also coupled to receive trigger signals based on a clocking signal received by the programmable analog circuit. Therefore, upon receiving a write cycle signal, the write synchronization circuit has the ability (if needed) to stall the microprocessor's operations until the optimum time for writing data into the register for controlling the programmable analog circuit.

Abstract: A method is described for decoding a signal in a noise environment using maximum likelihood soft decision decoding for input streams containing known data. ISI problems are ameliorated, and decoding is implemented by palmtop computers and devices of limited computational capability. Decoded signals make use of the (12, 8) Hamming Code for a MOBITEX application. A table with predetermined ISI values is downloaded from a host processor to an on-board DSP at runtime. Known information in the frame header is utilized to help determine unknown data. Decoding proceeds in one embodiment by finding codewords that minimize a sum corresponding to data values extracted from header information. Other tables generated for use contain soft decision information and FEC words. Minimizing data translation by using known data and other embodiments advantageously minimize computational resources required to decode data by maximum likelihood soft decision decoding.

Abstract: A method and system for performing computer implemented recognition is disclosed. In one method embodiment, the present invention first accesses user input stored in a memory of a mobile device. On the mobile device, the present invention performs a coarse recognition process on the user input to generate a coarse result. The coarse process may operate in real-time. The embodiment then displays a portion of the coarse result on a display screen of the mobile device. The embodiment further performs a detailed recognition process on the user input to generate a detailed result. The detailed process has more recognition patterns and computing resources available to it. The present embodiment performs a comparison of the detailed result and the coarse result. The present embodiment displays a portion of the comparison on the display screen.

Abstract: A processor power supply voltage controller. The controller includes a temperature sensor configured to sense a temperature of a processor and generate a temperature signal in accordance therewith. A regulator is coupled to provide a power supply voltage to the processor. The regulator is coupled to receive the temperature signal and control the power supply voltage to maintain a substantially stable crosstalk level within the processor.

Abstract: A method and logic for providing an asynchronous interface to a synchronous memory is disclosed. One embodiment of the present invention provides for a memory having a first logical unit which is operable to generate a synchronized clock signal in response to a chip select signal to the memory. The memory comprises synchronous memory arrays. The synchronized clock signal is input to the selected synchronous memory array. This allows an access to the synchronous memory to complete within a timing budget of the asynchronous interface. Furthermore, the memory has a second logical unit which is operable, in response to the chip select signal and a second signal input to the memory, to put an input/output bus coupled to the synchronous memory into a high impedance state by the end of the memory access. The second input signal may be a read enable or a write enable signal.

Abstract: A portable computer system that comprises dynamically adjustable brightness range settings and brightness control for providing improved user readability and prolonged component lifetime of the display screen. The main processor can change the range settings based on ambient light conditions or the user can perform the changes. The brightness level of the display changes according to a user selected setting within the range selected. The time required to implement the brightness change can be set to a value which can be configured by the user.

Abstract: A method and system for synchronizing updates of vertex data by a processor with a graphics accelerator module that is fetching vertex data is disclosed. The method and system comprises providing vertex array range (VAR) and writing vertex data into the VAR. The method and system includes providing a command into a command stream of the graphics accelerator module indicating that the vertex data has written into the VAR, and providing a fence condition based upon the command. A system and method in accordance with the present invention thus permits extremely high vertex processing rates via vertex arrays or vertex buffers even when the processor lacks the necessary data movement bandwidth. By passing indices in lieu of the vertex data, the processor is capable of keeping up with the rate at which a vertex engine of the graphics accelerator module can consume vertices.

Abstract: A method and a system for data transmission between a first electronic device and a second electronic device, wherein the second electronic device is in a sleep mode. Transmission of data between the first electronic device and the second electronic device occurs while a microprocessor in the second device is in sleep mode and the wireless transceiver is in a wake mode. The first electronic device transmits data signals and the second electronic device detects the transmitted signal. A base band processor in the second electronic device optionally determines if the signal is from a known source. If the first electronic device is a known electronic device, an interrupt signal is generated to wake up the microprocessor in the second electronic device. The wakened microprocessor opens a communication port and disables the wake-up interrupt. In yet another embodiment of the present invention, the data receive line is directly coupled to a line that triggers an interrupt when a signal is detected.

Abstract: A programmable analog system architecture and method thereof are described. The analog system architecture and method introduce a single chip solution that contains a set of tailored analog blocks and elements that can be configured and reconfigured in different ways to implement a variety of different analog functions. The architecture includes an array of analog blocks, including continuous time blocks and different types of switched capacitor blocks. The analog blocks can be electrically coupled to each other in different combinations to perform different analog functions. Each analog block includes analog elements that have changeable characteristics that can be specified according to the function to be performed. The architecture thereby facilitates the design of customized chips at less time and expense.