Abstract: A method for utilizing a delay lock loop to cover a wide delay range. In one method embodiment, the present invention receives a reference clock pulse. Next, in a first loop, a phase variation is adjusted between the feedback clock pulse and the reference clock pulse utilizing a coarse delay in conjunction with a first fine delay. The resulting pulse is then output to a chip delay and then sent back to the delay lock loop as a feedback clock pulse. Additionally, in a second loop, the phase variation is adjusted between said second loop and said first loop utilizing the coarse delay in conjunction with a second fine delay, wherein the second fine delay has a delay range for adjusting the phase variation which overlaps the delay range of the first fine delay of the first loop.

Abstract: A memory device having a plurality of multi-bit cells that are programmed with interlaced data provide superior read access time. The multi-bit cells are read by reading the first bit of each of the plurality of cells sequentially using a first reference voltage then reading the second bit of a first subset of the plurality of cells sequentially using a second reference voltage then reading the second bit of a second subset of the plurality of cells sequentially using a third reference voltage. The second reference voltage being higher and the third reference voltage being lower than the first reference voltage.

Abstract: A method and a system for using a graphics user interface for programming a microcontroller. The microcontroller design system includes a device editor system with integrated datasheet information and having three independent, but integrated workspaces to provide a programmer an organized way of displaying device editor information. The three workspaces include a user module selection workspace, a user module placement workspace and a user module pin out workspace for allowing the programmer to select desired function components for a target microcontroller device. The user module selection workspace allows the programmer to select desired components from a list of user modules and the placement workspace allows user modules to be placed in allowable hardware resources. The user module pin out workspace provides the programmer with the means to retrieve pin out information on the selected user modules that constitute the desired target microcontroller device design.

Abstract: A system and method for displaying a customized register name, an associated physical address, and an associated value in a software design tool. The customized register name identifies a user module and a configuration register of the user module. The user module is a circuit design to be realized in a programmable electronic circuit. The customized register name can be automatically generated based on the user module name and the configuration register name. The customized register name can also be modified as a unique identifier by a user. The physical address and value of the configuration register can be automatically updated based on modifications of the user module and/or hardware resources assigned to the user module.

Abstract: A system for dynamically building a graphical user interface of a target device in a home audio video network. The system includes a computer system within a host device coupled to the home audio video network, the computer system having a processor coupled to a memory via a bus. The computer system is configured to implement a graphical user interface for one or more target devices coupled to the home audio video network by executing software stored in the memory, wherein the software causes the computer system to perform the steps for dynamically building the graphical user interface. The steps include enumerating units on the network, each unit being a software based representation of a target device. The subunits within each unit are enumerated, the subunits being software based representations of functions of the target device. The requirements for a GUI (graphical user interface) is then determined for each subunit.

Abstract: A system and method for installing an application on a client device (e.g., a palmtop computer system) communicatively coupled to a host device (e.g., a host computer system). Instead of transferring an application to the client device from another client device, the client device receives a description of the application from the other client device. When the client device and the host device are synchronized, the description is automatically communicated by the client device to the host device, which is also in communication with a source (e.g., an application source). Additional information, such as the type of hardware or the type of operating system used by the client device, is also automatically communicated to the host device by the client device. The host device communicates to the source a specification comprising the description of the application as well as the additional information pertaining to the client device. The host device receives from the source a software element (e.g.

Abstract: An apparatus and method for a semiconductor device with reduced gate capacitance. Specifically, an n-channel or p-channel junction field effect transistor (JFET) is described comprising an appropriately doped substrate forming a drain region, an epitaxial layer formed on top of the substrate, a control structure comprising a gate region implanted into the epitaxial layer, a source region sharing a p-n junction with the gate region, and an altered epitaxial region. The altered epitaxial region is formed by implanting either n− or p− dopants directly below the gate region of either the n-channel or p-channel JFET for widening a depletion region surrounding the gate region. The enlarged depletion region reduces the gate capacitance of the JFET between the gate and drain regions.

Abstract: A programmable logic device includes a plurality of clusters of logic elements. Each of the clusters may include a respective programmable interconnect matrix with each of the logic blocks of each cluster being coupled to the respective programmable interconnect matrix of the cluster. Each of the clusters may be symmetrically coupled to a row and a column of a global routing matrix. The row and the column of the global routing matrix may themselves be symmetrical and each row and/or column may be coupled to an input/output cell of the programmable logic device. The global routing matrix may comprise a plurality of programmable interconnections.

Abstract: Method and system for latency-independent peripheral device identification. In one embodiment, a computer system receives an interrupt from a peripheral device coupled to a computer system communications port. In response, an interrupt notification message is posted alerting a notification handler running on the system. It is determined whether the interrupt is indicates peripheral class compliance. In one embodiment, communications port device sense pin voltage is determinative. If the interrupt indicates peripheral class compliance and the communications port is inactive, the port is opened, and inquiry sent to the peripheral device via the open port. The computer system then waits for response from the peripheral device. If response is received within a predetermined time, identification is posted based on the response, including peripheral device classification information, so that a software handler registered with the operating system can handle the identification message when received.

Abstract: A method of routing a received message to a proper software controller in a home audio/video network of connected network devices. A message is received from a network bus by an intelligent device coupled to the network bus, wherein the intelligent device includes a memory having stored therein a plurality of software controllers for communicating with a plurality of network devices. The intelligent device examines the received message to determine a memory space indication and a source device identification stored therein. The intelligent device then determines whether any software controllers associated with the device match the memory space indication. Provided that only one software controller matches the memory space indication, the received message is dispatched to the one software controller.

Abstract: A system and method for changing data displayed on a touch-sensitive display screen. The present system and method recognize handwritten strokes made with a stylus on the touch-sensitive display screen of a PDA or palmtop computer in order to alter or correct displayed data. In one mode of operation, computer controlled association of the location of the handwritten strokes on the display screen with one or more of the displayed characters will result in automatic replacement of those characters by the handwritten strokes. In a second mode of operation, matching at least one of the handwritten strokes with one character of the displayed data will result in replacement of one or more characters of the displayed data with the handwritten characters. With the present system and method, the number of steps required to alter displayed data is reduced to the number of handwritten strokes. A significant reduction in time and effort as well as a simplification in application is therefore offered.

Abstract: A method and computer aided system for predicting the reliability of oxide-nitride-oxide (ONO) based non-volatile memory. ONO memory devices may be programmed. Margin voltages may be recorded initially, and during baking at 100 degrees C. and 300 degrees C. From this data, constants and activation energy may be determined through a first formula. Frenkel-Poole activation energy may be determined. Through the use of a second formula, decay time of the information stored in the ONO memory may be predicted from the activation energy. The first formula may also be used to predict the decay time. The two decay time predictions may be compared to establish confidence. In this manner, data retention of an ONO memory may be reliably predicted.

Abstract: A ball grid array (BGA) package is disclosed. An interconnect structure is formed on a substrate that electrically connects the electrical device to be housed in the BGA package to the solder balls thereon. Contact pads are formed over the top surface of the substrate. These contact pads electrically connect to the interconnect structure. A layer of solder mask is formed over the substrate that includes openings that overlie the contact pads. The BGA is then completed using conventional process steps. Thereby, a BGA package is formed that includes contact pads disposed such that the contact pads are accessible from the top of the BGA package, making these contact pads easily accessible. Thus, when the BGA is attached to a circuit board, connection to circuits of the electrical device is obtainable.

Abstract: In a home audio video network of connected network devices, a method of routing a received message to a software controller. An incoming message is received from a network bus by an intelligent device having a plurality of software controllers for communicating with a plurality of network devices. The incoming message are examined in a first message handling unit to determine a corresponding one of the plurality of software controllers within the intelligent device. The incoming message are dispatched to the corresponding one software controller using the first message handling unit. An outgoing message is received from one of the plurality of software controllers in a second message handling unit. The outgoing message is examined to determine a corresponding one of the plurality of network devices. The outgoing message is dispatched to the corresponding one network device with the first and second message handling units functioning independently.

Abstract: One embodiment of the present invention provides a method of fabricating a cathode requiring relatively few and somewhat simple steps. One embodiment also provides a method of fabricating a cathode which eliminates a direct via masking step. One embodiment provides a method of fabricating a cathode which reduces manufacturing costs and increases the efficiency and productivity of manufacturing lines engaged in cathode fabrication. One embodiment provides a method of fabricating a cathode, which reduces the unit cost of thin CRTs. In one embodiment, a novel method effectuates fabrication of a cathode by a process requiring relatively few and somewhat simpler steps. Importantly, in the present embodiment, the requirement for at least one conventionally required direct via masking steps is eliminated. This effectively eliminates or substantially reduces associated costs, concomitantly reducing process completion time.

Abstract: An embodiment of the present invention provides a method of fabricating a cathode requiring relatively few and somewhat simple steps. One embodiment provides a method of fabricating a cathode in which the passivation layer and the metallic gate chromium are masked and patterned simultaneously. The method effectuates patterning of the passivation layer as necessary and simultaneously fixes a location for both access spots and inter-pixel electrical isolation areas to chromium constituting the metallic gate. Importantly, the present implementation effectively eliminates a conventionally requisite subsequent metallic gate chromium masking and etching step. Advantageously, this effectively streamlines and economizes cathode fabrication. The present embodiment thus reduces manufacturing costs and increases the efficiency and productivity of manufacturing lines engaged in cathode fabrication. This effectively reduces the unit cost of flat panel CRTs.

Abstract: A normally “off” enhancement mode junction field effect transistor (JFET) is disclose. The JFET has a low threshold voltage in the range of 0.2 to 0.3 volts and a low on resistance. The Drain-to-Source voltage drop is less than 0.1 volt at a drain current of 100 amperes.

Abstract: A method of providing and enabling a dynamic and scaleable system architecture for a computer system is disclosed. The method is executed on a computer system having a processor, a computer readable memory, and an adapter for receiving a module that will add functionality to the computer system. The processor is coupled to the computer readable memory and to the adapter. The method is implemented on the computer system by storing program instructions on memory and executing them via the processor in conjunction with other components of the computer system. The method comprises several steps, starting with a first step of detecting the availability of a new function. Next, an input interface specification and an output interface specification for the new function is received by the computer system.

Abstract: Sharing information between a host computer system and a peripheral computer system. Conduit programs running simultaneously on the host computer system synchronize information between the two computer systems. The conduits initiate multiple interleaved requests to transfer information across a single communication link between the two computer systems. Thus, the conduits initiate time multiplex transfers across the single communication link. In general, one or more conduits can perform a non-transfers task while another conduit can simultaneously perform a transfer over the host-peripheral communication link.

Abstract: An integrated position determination system and communication system is disclosed that includes an antenna and that includes position signal processing circuitry for determining position. The integrated position determination system and communication system also includes a radio for communicating with other position determination systems that is coupled to the position signal processing circuitry and a power supply. The integrated position determination system and communication system also includes a range pole to which the other components of the integrated position determination system and communication system are attached. The components of the integrated position determination system and communication system are located such that the system is both horizontally balanced and vertically balanced. More particularly, the integrated position determination system and communication system is horizontally balanced about the centerline of the range pole and is vertically balanced about a carrying point.