Abstract: A scaleable priority arbiter for arbitrating between multiple FIFO entry points of a network interface card (NIC). The circuit provides a separate FIFO entry point circuit within the NIC for each data packet priority type. Exemplary priority types, from highest to lowest, include isochronous, priority 1, priority 2, . . . , priority n. A separate set of FIFO entry points are provided for NIC transmitting (Tx) and for NIC receiving (Rx). For each of the Tx FIFO entry points, a single Tx entry point register is seen by the processor and multiple downlist pointers are also maintained. The Tx entry point registers all feed a scaleable priority arbiter which selects the next message for transmission. The scaleable priority arbiter is made of scaleable circuit units that contain a sequential element controlling a multiplexer.

Abstract: A method and circuit for reducing the power up time of a phase lock loop (PLL). In one embodiment, the present invention cuts off a first voltage to the phase lock loop thereby powering down the phase lock loop. In power down, a second voltage is utilized to maintain the power requirements of the filter node within the phase lock loop while the other components of the phase lock loop are powered down. The PLL is now in a power down mode. The present invention then restores the first voltage to the PLL. Once the internal components of the PLL stabilize, the second voltage is disengaged from the filter node wherein the phase lock loop is powered up to operational power.

Abstract: The present invention provides a novel method for a driving a cable and a cable driver circuit that are relatively insensitive to parasitic capacitance. The present invention provides a cable driver circuit and a method of driving a cable that is relatively insensitive to variations in load impedance. In one embodiment, a source-follower circuit with a complementary metal oxide semiconductor (CMOS) implementation effectuates a cable driver circuit, Which needs no operational amplifier for its functionality. In one embodiment, the cable driver circuit utilizes an internal precision voltage reference with a two-stage CMOS differential voltage amplifier, and a CMOS current mirror to generate a constant current source. The resulting constant current source delivers a signal compliant with the ITU-G703 specification, and which is stable and compliant over a wide range of load impedance values and associated capacitive milieus.

Abstract: A memory resident circuit cell model for characterizing an integrated circuit cell. The present invention comprises a first aggregate value representing a best case corner and a second aggregate value representing a worst case corner. In the present embodiment, the first and second aggregate value comprise a first delay representation accounting for timing variations of the cell relative to cross-coupling within the cell and a second delay representation accounting for timing variations of the cell relative to over-the-cell-routing-coupling. The first and second aggregate value further comprise a third delay representation accounting for timing variations of the cell for pin-input-capacitance and a fourth delay representation accounting for timing variations of the cell relative to delays due to near simultaneous input switching.

Abstract: Apparatus and method for providing DMA transfers between an adapter card with or with out DMA capabilities and a system CPU with DMA capabilities. An adapter DMA controller circuit resides between the system CPU and the adapter card. This adapter DMA controller allows the system to run in immediate mode which allows the system CPU to talk to the adapter card as if the adapter DMA controller was not there. The system can also run in DMA mode. In this mode the system CPU sets up the system DMA controller and the adapter DMA controller. The adapter DMA controller takes over sending or receiving data to the adapter card and then requesting a DMA transfer with the system DMA controller. The transfer of data between the adapter DMA controller and the adapter does not use any system CPU resources such as the data and address busses. The system CPU is free to use the system resources to continue operation.

Abstract: An antenna configuration for storing and deploying an antenna used with a hand-held wireless device, and method thereof. The device housing has a molded opening for holding a stylus element used with the device. The antenna is also stored in the housing within the molded opening. When the stylus is removed from the molded opening, the antenna can slide within the opening to a position in which it protrudes at one end from the housing. Thus, the antenna can be stored where it is protected and out of the way. In addition, the current form factor (size, shape and appearance) of the hand-held device can be retained.

Abstract: An integrated circuit device includes an input circuit; logic circuitry coupled to the input circuit; an output circuit coupled to the logic circuitry; and a select circuit coupled to the input circuit, output circuit and logic circuitry. The select circuit generates a select signal that causes the input circuit, output circuit and logic circuit to operate according to a first state or a second state. The output buffer is configured to receive the select signal which selects output buffer operation at the first state or the second state. The output buffer is also configured to maintain a constant slew rate while operating in either the first or second state.

Abstract: A method and system providing simultaneous data entry for a computer system having both on-screen keyboard entry and mechanisms for handwriting recognition entry. In one embodiment, a portable or palmtop computer system contains a flat panel display screen capable of displaying thereon a keyboard image (“virtual keyboard”). Characters can be entered into the computer system by a user interacting with (e.g., tapping) the displayed characters of the virtual keyboard. The computer system also provides a handwriting recognition mechanism (e.g., digitizer pad) whereby characters are recognized based on a user drawing strokes on the pad. In accordance with the present invention, the virtual keyboard and the handwriting recognition mechanism are simultaneously active for data entry. Therefore, the computer system can accept character entry from the handwriting recognition mechanism while the virtual keyboard is displayed and active and capable of providing character entry itself.

Abstract: An asynchronous memory device includes parallel test circuitry configured to interface with a single-ended output data path of the memory device and, in some cases, to provide a measure of a slowest cell access time for the memory device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the memory device and to provide first output signals indicative of logic states of the plurality of cells; and second circuitry configured to receive the first output signals and to produce a second output signal indicative of the logic states of the first output signals therefrom. For example, the first circuitry and the second circuitry may be configured as a wired NAND and wired NOR combination. In some cases, one or more of the cells may be included within a redundant row or column of the memory device.

Abstract: A matching circuit for coupling a conventional metal-oxide semiconductor field effect transistor (MOSFET) driver to the gate of a junction field effect transistor (JFET). A driver circuit optimized for driving a MOSFET is combined with a matching circuit to provide gate drive for a JFET. The matching circuit comprises a resistor and capacitor in parallel. For driving enhancement mode JFETs having a gate grid array structure and a pinch-off voltage greater than 0.4 volts, the range of resistor values is 10 to 200 ohms, and the range of capacitor values is 1 to 100 nF. For devices having a pinch-off voltage less than 0.4 volts, the range of resistor values is 100 to 2000 ohms. The matching circuit may further include a diode to provide a bias.

Abstract: A method for programming a memory device is disclosed. In one method embodiment, the present invention receives a measurement from a temperature sensor located near a non-volatile programmable memory device. Next, a transformation is accessed. Then, the measurement from the temperature sensor is processed in conjunction with the transformation to establish a programming time for a memory device as a function of a programming voltage and the temperature of the memory device. The programming voltage is then applied to the memory device for the length of time specified by the programming time during the programming pulse of the memory device to accurately program the device using an optimum amount of current.

Abstract: The present invention enables automatic setting a natural language default selection in a video presentation device and facilitates easy manufacturing adjustments to accommodate a variety of possible natural language preferences that exist among different geographical areas. A video tuner natural language default selection system of the present invention facilitates reception of video communication signals (e.g., a television broadcast signal) and tuning into particular geographical default natural language information included in the video communication signal. A tuner controller provides instructions to a tuner on the selection of the geographical default natural language information for communication to downstream components. A memory stores information for the tuner controller, including a geographical default natural language indicator for referring to a geographical natural language table comprising natural language selections.

Abstract: Methods and systems for improving the storage capacity and data throughput of a digital mass storage device. The novel optimizations can be applied to a disk drive, either a hard disk drive or a disk drive having removable media, such as magnetic and optical disk drive technologies. The present invention provides at least two disk drive heads for reading and writing information from two different spinning media surfaces, e.g., platters or disks. If the disk is a read-only device, then the heads only perform the read function. A constant angular velocity drive mechanism is used meaning the rotational speed of the media is constant regardless of the head's position with respect to the media. In operation, during a media transfer, the first head accesses data by starting at the outside regions (“high track rates”) of the disk media and traversing inward towards the inner regions (“low track rates”).

Abstract: A device for executing an event thread. The device has programmable logic for storing data to define a number of states in an event thread to be executed in the event engine. The device also has execution logic coupled to the programmable logic. The execution logic is configurable to execute the current state and re-configurable to execute the next state, in response to data from the programmable logic. In this fashion, the next state may be executed by re-configuring the execution logic. The device also has transition logic coupled to the programmable logic. The transition logic causes the next state in the event thread to be entered by loading new data from the programmable logic. Therefore, the execution logic is re-configurable during execution of the event thread.

Abstract: A charging apparatus for a portable rechargeable electronic device is described. The charging apparatus contains a substantially flat conductive surface for receiving the electronic device placed thereon. Small conducting nodules of the device mate with the conductive surface to charge a rechargeable battery of the device. Charging may commence upon placement of the device. The surface may contain a positive and a negative electrode. The surface may have lips placed around the perimeter to form a tray like structure. Synchronization with a host system and the device may occur wirelessly.

Abstract: An embodiment of the present invention provides a method and apparatus that effectuates a direct functional interface directly with individual constituent subcomponents of the internal die component, or with particular circuit nodes or conductive trace locales of the surface mount package, without high frequency signal degradation or other electrical problems. An embodiment of the present invention also provides a method and apparatus that effectuates testing access, directly to the internal die component of the surface mount package or to a particular circuit node or conductive trace locale of the surface mount package, enabling performance evaluation and system debugging. Further, an embodiment of the present invention provides a method and apparatus that effectuates integration of surface mount package with an opto-electronic package. Further still, an embodiment of the present invention provides a method and apparatus that achieves these advantages with minimal cost.

Abstract: A method and system for eliminating post etch residues is disclosed. In one method embodiment, the present invention recites disposing a surface, having post etch residues adhered thereto, proximate to an electron beam source which generates electrons. The present method embodiment then recites bombarding the post etch residues with the electrons such that the post etch residues are removed from the surface to which the post etch residues were adhered.

Abstract: In one embodiment, the present invention recites forming a number of first openings in a first substrate. The present embodiment then recites forming a copper region within each first openings during a damascene process, wherein each copper region has a top surface. The present embodiment then disposes a dielectric layer proximate to the top surface of each of the first copper regions during the damascene process. After depositing a second substrate over the dielectric, a number of second openings in a second substrate are made. Next, a number of second copper regions are formed in the second openings, during the damascene process. The dielectric region is thus disposed between the first copper regions and the second copper regions. In so doing, the dielectric region forms a dielectric barrier between the first copper regions and the second copper regions such that a metal-insulator-metal (MIM) capacitor is formed during a damascene process.

Abstract: A computer implemented method of implementing a touch screen user interface in conjunction with sensors for a computer system. A touchscreen area is provided for accepting text input strokes and for accepting icon manipulation strokes. A sensor is provided adjacent to the touchscreen area for registering sensor actuations from a user. In implementing the user interface, user input strokes are accepted into the touchscreen input area. User input strokes into touchscreen input area are interpreted as text input strokes when the sensor is actuated by the user during the user input strokes. User input strokes into the touchscreen input area are interpreted as icon manipulation strokes and not text input strokes when the sensor is not actuated by the user during the user input strokes.

Abstract: Architecture to fragment transmitted transmission control protocol (TCP) packets to a requested window size. Specifically, one embodiment of the present invention includes a method for implementing transmission control protocol segmentation within hardware. The method includes the hardware, implemented step of downloading a payload header of a data payload stored within memory of a host device. Furthermore, the method also includes the hardware implemented step of downloading a plurality of data segments of the data payload. Additionally, the method includes the hardware implemented step of repeatedly modifying the payload header in order to generate a plurality of frame headers which correspond to the plurality of data segments.