Abstract: A two-pass Multiplier/Accumulator Circuit is provided which performs various arithmetic operations on operands contained within an X Register 10 (FIG. 1) and a Y Register 20 and places the result in an Accumulator Register 40. The arithmetic operations are carried out by passing the product of the operands successively through an array of adders in the Adder unit 34. Each adder adds an appropriate multiple of the contents of the X Register to the Accumulator 40 or to the output of the previous adder. The multiples are selected according to the contents of the Y Register.The X and Y Registers are fully buffered so that additional data transfers and functions may be performed while an arithmetic operation is in progress in a "pipeline" manner.The circuit is also capable of indicating the maximum or minimum value in a sequence of numbers in response to a single computer instruction to the circuit.

Abstract: In an electronic system, such as a digital data processing system, comprising a number of circuit boards, each circuit board being of a particular functional type and also uniquely identifiable by a manufacturing revision number, there is provided a status detection circuit for polling various programmable status information from the board, including a unique board identity number and the manufacturing revision number. The status detection circuit includes a microcomputer (60, FIG. 2) on each board 50. The data inputs of the microcomputer are responsive to a unique combination of switches (e.g., 42) representative of the manufacturing revision number. Other microcomputer inputs are responsive to a unique combination of edge connectors (e.g., 47) for uniquely identifying the particular board in the system. Another microcomputer input is responsive to an on-board status indicator, such as an LED.

Abstract: A high speed countdown counter (FIG. 7) capable of operation at up to 10 MHz is provided which comprises a number of stages each comprising a flip flop (134, 136; 144, 146; etc.), a preset data input (IN1, IN2, etc.), a carry input (N11, N10, etc.), a data output (N5, N4, etc.), and a carry output.Dynamic Depletion Mode (DDM) transistors (129, 139, etc.) are employed to reduce charging time at inter-stage nodes and thereby improve speed, while minimizing circuit size and power requirements.A look-ahead feature enables early detection of an "all zero minus one" count and enables the presetting of data into the counter simultaneously with the generation of a "carry out" signal from the counter. Various internal counter control signals are delayed by couplers driven by a two-phase non-overlapping clock, in order to allow for signal propagation time through the corresponding circuit elements.

Abstract: A TV timebase circuit includes a vertical sync counter in the form of a ten-bit ripple-through counter. Additional logic circuitry including a pair of divide-by-four counters, a latch, a D flip-flop, and associated AND, NAND, and invertor gates are also provided. The circuit is responsive to a multiple of the horizontal frequency and to vertical sync pulses and is capable of automatic recognition of 525 or 625 line standard. The logic includes a mechanism for locking out the vertical counter's 525 count when operating in the 625 mode. The latch, in association with one of the divide-by-four counters serves a "fly wheel" sync function, whereby a predetermined number of "matches" must be recognized to lock the circuit into a given mode, and whereby a predetermined number of "mis-matches" must occur to drop the circuit operation from the locked-in mode. Several outputs are taken off the vertical counter to operate ramp drive and blanking functions of the TV vertical sweep generator.

Abstract: A single-chip microcomputer includes a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), and four I/O ports (11-14). The serial I/O communication logic includes a control and status register (46), one bit (WU) of which may be utilized, when the microcomputer is connected in a distributed processing system having a shared serial communication line, to indicate that the CPU wishes to ignore a message not of interest to it. When the serial communication line again becomes free, the WU control bit is reset, enabling the CPU to intercept a new message of interest.

Abstract: A microprocessor comprises an internal address bus having a first portion (2,4) having a plurality of conductors carrying the low order address byte and a second portion (10) having a plurality of conductors for carrying the high order address byte. The microprocessor further comprises a plurality of registers, including an incrementor (12,13), a program counter (14,15), a temporary register (16,17), a stack pointer (18,19), an index register (20,21), and an accumulator (22,24), each comprising a pair of 8-bit registers for temporarily storing information. An arithmetic logic unit (28) performs computational operations on digital information within the microprocessor. The microprocessor includes a pair of internal data buses (6,8) each having a plurality of conductors for conducting digital information within the microprocessor. Means are provided for coupling selected ones of the registers, or the high or low order portions thereof, to the first and second data buses.

Abstract: A bit-oriented data link controller provides the interface between a microcomputer or terminal and a data communications link. The data link controller is capable of accommodating the three most commonly available bit-oriented data link control protocols, namely Synchronous Data Link Control SDLC, High Level Data Link Control HDLC, and Advanced Data Communications Control Procedure ADCCP. The data link controller provides the data communications interface for both primary and secondary stations in stand-alone, polling, and loop configurations.

Abstract: A microprocessor is disclosed which includes a timer and one or more capture registers. The timer is a counter which is incremented continuously at a fixed clock rate for providing a real time reference. Each capture register is loaded directly from the timer output when a triggering signal appears on a specific input pin, thus recording the time of the occurrence of the triggering signal without interrupt or software intervention.

Abstract: A single-chip microcomputer comprises a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), and four I/O ports (11-14).The serial I/O communication logic includes a shift register (RBA-RBH, FIG. 8J) to separate the data and clock signals in a Manchester-encoded data stream. The Manchester encoding is adaptable to any data rate simply by changing the frequency of a high speed clock associated with the shift register.

Abstract: An analog-to-digital converter includes a first and a second comparator. The first comparator generates a plurality of quantizing outputs defining voltage gaps and also has first and second reference current outputs whose magnitudes are representative of which voltage gap encompasses the analog input voltage and a third reference current output whose magnitude is representative of the voltage gap width. A first encoder receives the quantizing outputs of the first comparator and generates a binary number which represents which of the voltage gaps the analog input voltage is encompassed by. The reference current outputs of the first comparator are input to a reference voltage level shifting circuit whose shifted reference output voltage is provided as an input to a second comparator which compares the analog input with a plurality of internal reference voltages which form a second continuous range of voltage gaps.

Abstract: A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA.The peripheral interface adaptor includes a plurality of system data bus buffer circuits coupled to a system data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. The direction of data flow in the peripheral data bus is controlled by a data direction register. Data from the system data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, a data direction register and a data register. Data from the peripheral data bus, the data direction register and the control register are transferred via an output bus to the system data bus buffers.

Abstract: An analog-to-digital converter includes a first and a second comparator each of which receives an analog input. The first comparator generates a plurality of reference voltages which establish a first continuous range of voltage gaps. The first comparator has a plurality of quantizing outputs, one of which will be at a logical one and the rest of which will be at logical zeros in order to indicate which of the voltage gaps encompasses the analog input voltage. The first comparator also has first and second reference current outputs whose magnitudes are representative of which voltage gap encompasses the analog input voltage and a third reference current output whose magnitude is representative of the voltage gap width.

Abstract: An analog-to-digital converter includes a first comparator which receives an analog input. The first comparator generates a plurality of reference voltages which establish a first continuous range of voltage gaps. The first comparator has a plurality of quantizing outputs, one of which will be at a logical one and the rest of which will be at logical zeros in order to indicate which of the voltage gaps encompasses the analog input voltage. The first comparator also has a reference current output whose magnitude is representative of which voltage gap encompasses the analog input voltage. A first encoder receives the quantizing outputs of the first comparator and generates a binary number which represents which of the voltage gaps the analog input voltage is encompassed by and which constitutes the most significant bit group of the binary digital representation of the analog input voltage. A voltage subtractor circuit receives as inputs the reference current output of the first comparator and the analog input.

Abstract: A circuit and a method for adding an 8-bit operand to a 16-bit operand are disclosed such that the number of machine cycles required by a data processor to perform such an addition is reduced. The 8-bit operand and the least significant byte of the 16-bit operand are added together within an 8-bit adder circuit to generate the least significant byte of the result. Simultaneously, the most significant byte of the 16-bit operand is stored in a temporary register and is also input to an increment/decrement network. The adder circuit, after a given delay time, generates a carry signal depending on whether a carry-out was produced by the addition. The carry signal and the sign bit of the 8-bit operand control the mode of operation of the increment/decrement network and determine whether the increment/decrement network or the temporary register will be selected to provide the most significant byte of the result.

Abstract: A divide circuit is provided for dividing an input signal of frequency N by the quantity M+0.5, where N is any positive number and M is an integer. In one embodiment a clock signal operating at a frequency of 3.5 megahertz is divided by 3.5, yielding an output signal of 1 megahertz. Additional logic means may be provided responsive to a control signal for dividing the input signal by the quantity M+1 for a given state of the control signal.

Abstract: A circuit for extracting a low frequency signal component from a composite signal is disclosed which uses a digital averaging technique for filtering out higher frequency components. An analog to digital converter receives a composite analog signal and provides a digital output signal. The composite analog signal is sampled during periodic intervals or sample periods. The digital output signal of the analog to digital converter is coupled to one input port of an adder/subtractor circuit and to the input of a sample register. The sample register stores the digital output signal and outputs the stored signal, delayed by a predetermined number of sample periods, to a second input port of the adder/subtractor. A storage register is used to store a running average which is equal to the sum of the digital signals received during the most recent predetermined number of sample periods. The average signal stored by the storage register is fed back to a third input port of the adder/subtractor.

Abstract: A crystal oscillator is provided a portion of which is fabricated in monolithic integrated circuit form. The circuit is temperature-compensated and utilizes a single 5 volt DC power supply compatible with NMOS and TTL voltage levels. The duty cycle of the oscillator may be varied between approximately 30 and 70 percent.

Abstract: An improved read circuit for use with a magnetic read transducer in a magnetic recording system in which the read transducer generates an alternating current playback signal having alternating positive and negative peaks. The read circuit comprises an active differentiator responsive to the playback signal for producing a differentiated signal having positive and negative values with zero crossings in time coincidence with the positive and negative peaks of the playback signal, and a differential comparator for generating an intermediate playback signal having a first value when the differentiated signal is positive and having a second value when the differentiated signal is negative and for generating the complement of the intermediate signal.

Abstract: The peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA.A peripheral interface adaptor includes a plurality of data bus buffer circuits coupled to a bidirectional data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral system data bus. A direction of data flow at the peripheral interface data bus is controlled by a data direction register. Data from the data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, a data direction register and a data register. Data from the peripheral data bus, the data direction register, and the control register are transferred via the output bus to the data bus buffers.

Abstract: A CCD (charge coupled device) RAM (random access memory) includes a plurality of "rings" of serially connected CCDs in which digital information recirculates. A combinational decoder selects one of the plurality of rings by decoding a first group of binary address inputs. Each ring includes a plurality of input/output circuits coupled to associated "taps", each tap being coupled between an input and an output of a CCD regeneration cell. An address addition circuit includes a counter which counts at the same rate that data shifts through each of the rings and has a plurality of taps spaced at the same intervals (numbers of intervening CCD cells) as the taps in each of the rings. The counter outputs are decoded to provide a first internal address corresponding to the location of a fictitious tag bit in a ring with reference to an initial reference bit in a ring.