Abstract: A CMOS regulated constant current circuit includes a first reference circuit producing a reference voltage applied to one input of an operational amplifier. The output of the operational amplifier is connected to the gate electrode of a reference field effect transistor having its source connected to ground and its drain connected to the other input of the operational amplifier and to one terminal of a control resistor, the other terminal of the reference field effect transistor being coupled to a plurality of CMOS transmission gates. Each of the CMOS transmission gates can controllably be switched on independently in order to apply the operational amplifier output voltage to a respective one of a plurality of output field effect transistors of the same conductivity type as the reference field effect transistor and each having its source connected to ground.

Abstract: An interface adaptor couples peripheral equipment to a bidirectional data bus and an address bus of a digital system. A plurality of interrupt sources are provided on such an interface adaptor circuit. A status bit in a status register of the interface adaptor is provided which contains a logical state indicative of a logical ORing of the plurality of interrupt sources on the interface adaptor circuit.

Abstract: A multiple-generating register generates one of several possible multiples of a binary number which is input thereto depending upon the informational content of a 3-bit control signal. For each data stage there exists a data selector circuit, a master/slave circuit, and an output buffer circuit. The device can be configured as an inverting shift register for test and diagnostic purposes. The device is implemented in current mode logic, and a portion of the circuitry operates on differential level signals for increased operational speed and efficiency.

Abstract: A uniphase charge transfer device comprises a plurality of electrode pairs disposed over a layer of gate oxide which overlies a semiconductor substrate. Within the substrate are a plurality of first conduction regions which are doped to a conductivity type opposite to that of the substrate. The first conduction regions underlie the separations between electrode pairs, and each one is electrically connected to one member of each electrode pair. A plurality of second conduction regions in the substrate are of the same conductivity type as the substrate but are of a substantially greater density of impurity atoms, and each of the second conduction regions underlies a portion of the other member of each electrode pair. A single clock line is connected to that member of each electrode pair which overlies the second conduction region. By alternatingly applying a predetermined voltage to the single clock line, charge packets representing information are moved unidirectionally through the device.

Abstract: A time-independent CCD charge amplifier comprises first and second CCD lines each having a plurality of electrode pairs disposed over a layer of silicon dioxide overlying a semiconductor substrate. Two clocks which are in a predetermined phase relationship with respect to one another are connected to alternate electrode pairs. The second CCD line further comprises a clocked-source charge injector, the input gate of which is electrically coupled to the signal source, which in a preferred embodiment comprises a surface potential tap in the first CCD line. According to a preferred embodiment, charge is non-destructively sampled from the first CCD line and is amplified by a predetermined factor in the second CCD line.

Abstract: A multiple-generating register generates one of several possible multiples of a binary member which is input thereto in response to a respective one of a plurality of multiple-generating commands. The multiple-generating register comprises a control circuit for generating the multiple-generating commands in response to a three-bit control signal and comprises further a plurality of selector latch logic circuits. Each selector latch logic circuit receives as a first input a respective bit of the input binary number and receives as a second input the next lowest order bit of the input binary number, except that the selector latch logic circuit which receives as a first input the lowest order bit of the input binary number receives as a second input a zero-valued binary bit. The plurality of selector latch logic circuits generate a binary number that is a multiple of the input binary number, which multiple is equal to the input binary number times .+-.1, .+-.

Abstract: High density data storage is permitted on magnetic disk by providing uniform length data sectors and by grouping a plurality of data sectors with a single header. Any data sector may be accessed through location of the desired group header and counting to the position of the sector.

Abstract: A logic level translator utilizes a TTL logic gate, a current switch, and a clamp circuit to convert CML level binary signals into TTL level binary signals. The translator provides isolation between the TTL ground and the CML ground in order to reduce noise in the CML portion of the circuit. The clamp circuit prevents a switching transistor in the current switch from reaching saturation, thereby increasing the speed of operation of the translator. A portion of the current switch provides a quick pulldown of a switching transistor in the TTL circuit to reduce noise in the TTL circuit.

Abstract: A locator pin is provided as part of an apparatus for maintaining accurate registration between a circuit board on which a conductive pattern is to be formed and a printing mask containing the image of the conductive pattern. The locator pin comprises a base member, an upright body member having a plurality of annularly arranged slots therein, and a threaded expansion pin fitting into the body member. The body member has a first cross-sectional area when the expansion pin is not screwed into it and a second cross-sectional area when the expansion pin is forcibly screwed into it. The first cross-sectional area of the body member is less than that of registration holes in the circuit board and printing mask, permitting the circuit board to be easily positioned adjacent the printing mask. The second cross-sectional area is at least as great as that of the registration holes so that the circuit board and printing mask are interlocked in accurate registration with one another.

Abstract: A magnitude comparison circuit compares two X-bit binary numbers and two Y-bit binary numbers when a mode control signal is in a first condition and generates outputs indicating the relative magnitudes of the X-bit binary numbers and the Y-bit binary numbers. The magnitude comparison circuit compares two Z-bit binary numbers when the mode control signal is in a second condition and generates an output indicating the relative magnitude of the Z-bit binary numbers, where Z equals the sum of X and Y.

Abstract: A multiple-generating register generates one of several possible multiples of a binary number which is input thereto in response to a respective one of a plurality of multiple-generating commands. The multiple-generating register comprises a control circuit for generating the multiple-generating commands in response to a three-bit control signal and comprises further a plurality of selector latch logic circuits. Each selector latch logic circuit receives as a first input a respective bit of the input binary number and receives as a second input the next lowest order bit of the input binary number, except that the selector latch logic circuit which receives as a first input the lowest order bit of the input binary number receives as a second input a zero-valued binary bit. The plurality of selector latch logic circuits generate a binary number that is a multiple of the input binary number, which multiple is equal to the input binary number times .+-.1, .+-.

Abstract: Thickness of a sheet being produced by an extruder is controlled in response to measurements of: sheet thickness, the speed at which material is fed through a screw of the extruder, as determined by screw speed, and the speed with which material is taken away from the extruder, as determined by sheet speed. Measured thickness is compared with a setpoint for sheet thickness and a determination is made as to whether the thickness is in a predetermined, deadband region relative to the setpoint, or if the sheet is out of the deadband because it is excessively thin or excessively thick. In response to the sheet thickness being in the deadband region, the screw speed is changed in response to a signal indicative of the product of sheet speed error and rate of change of screw speed with respect to sheet speed. Sheet speed is controlled by multiplying sheet speed error by a predetermined constant.

Abstract: A process monitoring and control system is provided for use in a tire calendering system producing a strip of rubber tire material comprising a layer of tire cord laminated between first and second layers of rubber. In a preferred embodiment, the thickness of the first rubber layer is measured by a single point radiation backscatter gauge at a point prior to its lamination with the tire cord and second layer. The thickness of the first layer is controlled to a desired target by means of a control loop including the single point gauge. The total thickness of the combined layers is measured at the calender output by a total thickness gauge. Gauge coordination means, including a delay means, are provided whereby measurements of the thickness of the first layer and of the combined strip are derived over the same longitudinal portion of the strip.

Abstract: A method of fabricating conductivity connected charge-coupled devices (C4D's) is disclosed wherein N+ barriers are ion-implanted in an N-type substrate and wherein P++ conductivity connecting regions are formed by diffusion of impurity atoms into the substrate. The process is compatible with the known silicon gate process, enabling semiconductor devices of other types and with different thresholds to be formed on the substrate at the same time the C4D's are fabricated.